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1. 发明申请

WO1997041597A1 SEMICONDUCTOR ISOLATION REGION BOUNDED BY A TRENCH AND COVERED WITH AN OXIDE TO IMPROVE PLANARIZATION 审中-公开
标题翻译：半导体分离区域，由铁素体覆盖并覆盖氧化物，以改善平面化
公开(公告)号：WO1997041597A1
公开(公告)日：1997-11-06
申请号：PCT/US1997003255
申请日：1997-03-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , HAUSE, Fred, N. , BANDYOPADHYAY, Basab , FULFORD, H., Jim , DAWSON, Robert , MICHAEL, Mark, W. , BRENNAN, William, S.
IPC分类号： H01L21/762
CPC分类号： H01L21/76205 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.
摘要翻译：提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。隔离过程导致在紧邻有源区域的场区域中形成沟槽。然而，这个沟槽并不完全穿过田野区域。通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

2. 发明申请

WO1998002917A1 METHOD FOR FABRICATION OF A NON-SYMMETRICAL TRANSISTOR 审中-公开
标题翻译：非对称晶体管的制造方法
公开(公告)号：WO1998002917A1
公开(公告)日：1998-01-22
申请号：PCT/US1997004991
申请日：1997-03-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , GARDNER, Mark, I. , WRISTERS, Derick, J. , FULFORD, H., Jim
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/0338 , H01L21/28123 , H01L29/7835
摘要： The method for fabrication of a non-symmetrical IGFET of the present invention includes providing a semiconductor substrate having an insulating film and a gate material. A first portion of the gate material overlying a first region of the semiconductor substrate is removed forming a first sidewall of a gate electrode. A dopant is implanted into the first region after forming the first sidewall. After the first region is implanted, a second portion of the gate material overlying a second region of the semiconductor substrate is then removed forming a second sidewall of the gate electrode. A dopant is implanted into the second region after forming the second sidewall. Spacers are formed adjacent to each of the sidewalls of the gate electrode. Then, a dopant is implanted into portions of the first and second regions of the semiconductor substrate outside the gate electrode and the spacers. In one embodiment of the invention, the first region is a heavily doped source region and the second region is a lightly doped drain region. In another embodiment of the present invention the first region is a lightly doped drain region and the second region is a heavily doped source region. In both embodiments, a part of the lightly doped drain region is retained beneath a spacer.
摘要翻译：本发明的非对称IGFET的制造方法包括提供具有绝缘膜和栅极材料的半导体衬底。去除覆盖半导体衬底的第一区域的栅极材料的第一部分，形成栅电极的第一侧壁。在形成第一侧壁之后，将掺杂剂注入第一区域。在植入第一区域之后，然后移除覆盖半导体衬底的第二区域的栅极材料的第二部分，形成栅电极的第二侧壁。在形成第二侧壁之后，将掺杂剂注入第二区域。隔板与栅电极的每个侧壁相邻形成。然后，将掺杂剂注入到半导体衬底的第一和第二区域的位于栅电极和间隔物外部的部分中。在本发明的一个实施例中，第一区域是重掺杂的源极区域，而第二区域是轻掺杂的漏极区域。在本发明的另一个实施例中，第一区域是轻掺杂漏极区域，第二区域是重掺杂源极区域。在两个实施例中，轻掺杂漏极区的一部分保持在间隔物的下方。

3. 发明申请

WO1998025182A1 RETICLE THAT COMPENSATES FOR LENS ERROR IN A PHOTOLITHOGRAPHIC SYSTEM 审中-公开
标题翻译：补偿光刻胶系统中的镜头误差的补充
公开(公告)号：WO1998025182A1
公开(公告)日：1998-06-11
申请号：PCT/US1997022616
申请日：1997-12-04
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , MOORE, Bradley, T. , DAWSON, Robert , FULFORD, H., Jim , GARDNER, Mark, I. , HAUSE, Frederick, N. , MICHAEL, Mark, W. , WRISTERS, Derick, J.
IPC分类号： G03F07/20
CPC分类号： G03F7/70433 , G03F1/70 , G03F7/70241
摘要： A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.
摘要翻译：掩模版（130）提供图像图案并补偿光刻系统中的透镜误差。使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。通过调节辐射透射区域（132,134）的配置（或布局），例如通过调节石英基底的顶表面上的铬图案，可以对掩模版进行结构上的修改。或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

4. 发明申请

WO1996039713A1 A METHOD OF FORMING HIGH PRESSURE SILICON OXYNITRIDE (OXYNITRIDE) GATE DIELECTRICS FOR METAL OXIDE SEMICONDUCTOR (MOS) DEVICES WITH P+ POLYCRYSTALLINE SILICON (POLYSILICON) GATE ELECTRODES 审中-公开
标题翻译：形成具有P +多晶硅（多晶硅）栅极电极的金属氧化物半导体（MOS）器件的高压硅氧烷（氧化物）栅极电介质的方法
公开(公告)号：WO1996039713A1
公开(公告)日：1996-12-12
申请号：PCT/US1996009216
申请日：1996-06-06
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , WRISTERS, Dirk, J. , FULFORD, H., Jim , KWONG, Dim, L.
IPC分类号： H01L21/314
CPC分类号： H01L21/28202 , H01L21/3144 , H01L29/518 , H01L29/6659 , Y10S148/118 , Y10S438/91
摘要： A silicon oxynitride (oxynitride) dielectric layer is presented using a process in which nitrogen is incorporated into the dielectric as it is grown upon a silicon substrate. The oxynitride layer is grown at elevated temperature and pressure in an ambient containing N2O and/or NO. An MOS gate dielectric is advantageously formed from the oxynitride dielectric layer with a sufficient nitrogen concentration near the interface between a boron-doped polysilicon gate electrode and the gate dielectric as to prevent boron atoms from penetrating into the gate dielectric. Further, the oxynitride layer contains a sufficient nitrogen concentration near the interface between the gate dielectric and a silicon substrate as to reduce the number of high-energy electrons injected into the gate dielectric which become trapped in the gate dielectric. Nitrogen atoms in the gate dielectric near the interface between the boron-doped polysilicon gate electrode and the gate dielectric physically block boron atoms, preventing them from penetrating into the gate dielectric. Nitrogen atoms and silicon atoms form strong Si-N bonds at the interface between the gate dielectric and the silicon substrate, helping ensure injected electrons are not easily trapped in the oxynitride dielectric layer.
摘要翻译：使用氮化硅（氮氧化物）电介质层，其中当氮化物在硅衬底上生长时将氮结合到电介质中。氧氮化物层在含有N 2 O和/或NO的环境中在升高的温度和压力下生长。有利地，由氮氧化物电介质层形成MOS栅极电介质，在硼掺杂多晶硅栅极电极和栅极电介质之间的界面附近具有足够的氮浓度，以防止硼原子渗入栅极电介质。此外，氧氮化物层在栅极电介质和硅衬底之间的界面附近包含足够的氮浓度，以减少注入到栅极电介质中的高能电子的数量，这些电子电子被俘获在栅极电介质中。掺杂硼的多晶硅栅电极和栅介质之间的界面附近的栅极电介质中的氮原子物理上阻挡了硼原子，从而阻止它们渗入栅极电介质。氮原子和硅原子在栅极电介质和硅衬底之间的界面处形成强的Si-N键，有助于确保注入的电子不容易被捕获在氮氧化物介电层中。

5. 发明申请

WO1998025183A1 INSPECTION OF LENS ERROR ASSOCIATED WITH LENS HEATING IN A PHOTOLITHOGRAPHIC SYSTEM 审中-公开
标题翻译：检查与光学加热系统相关的镜头误差
公开(公告)号：WO1998025183A1
公开(公告)日：1998-06-11
申请号：PCT/US1997023139
申请日：1997-12-04
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , MOORE, Bradley, T. , DAWSON, Robert , FULFORD, H., Jim , GARDNER, Mark, I. , HAUSE, Frederick, N. , MICHAEL, Mark, W. , WRISTERS, Derick, J.
IPC分类号： G03F07/20
CPC分类号： G03F7/70058 , G03F7/70591 , G03F7/70891
摘要： A method of inspecting a lens (16) includes projecting a first amount of radiation through a first test pattern (42, 44) and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern (52, 54) and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.
摘要翻译：检查透镜（16）的方法包括：通过第一测试图案（42,44）和透镜投射第一量的辐射，以提供与透镜的第一加热相关联的第一透镜误差，投射第二量的辐射通过第二测试图案（52,54）和透镜提供与透镜的第二加热相关联的第二透镜误差，并且使用第一和第二透镜误差来提供作为加热透镜的函数而变化的图像位移数据。以这种方式，可以对给定掩模版特有的局部透镜加热进行校正。该方法非常适合于光刻系统，如步进和重复系统。

6. 发明申请

WO1998002913A2 METHOD OF FORMING A GATE ELECTRODE FOR AN IGFET 审中-公开
标题翻译：形成IGFET的门电极的方法
公开(公告)号：WO1998002913A2
公开(公告)日：1998-01-22
申请号：PCT/US1997005089
申请日：1997-03-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , GARDNER, Mark, I. , WRISTERS, Derick, J. , FULFORD, H., Jim
IPC分类号： H01L21/033
CPC分类号： G03F7/70466 , G03F7/00 , H01L21/0337 , Y10S438/947
摘要： A method of forming a gate electrode for an insulated-gatefield-effectransistor (IGFET) is disclosed. The method includes forming a gate material for providing a gate electrode over a semiconductor substrate, forming a first mask over the gate material wherein the first mask includes an opening that defines a first edge of the gate electrode, removing a first portion of the gate material to form the first edge of the gate electrode as defined by the first mask, forming a second mask over the gate material after removing the first mask wherein the second mask includes an opening that defines a second edge of the gate electrode, removing a second portion of the gate material to form the second edge of the gate electrode as defined by the second mask, and removing the second mask. Thus, the gate electrode is defined by a lateral displacement between the openings in the first and second masks. Preferably, the first and second masks are photoresist, and the length between the first and second edges of the gate electrode is less than the minimum resolution of a photolithographic system used to pattern the masks.
摘要翻译：公开了一种形成绝缘栅场效应晶体管（IGFET）的栅电极的方法。该方法包括形成用于在半导体衬底上提供栅电极的栅极材料，在栅极材料上形成第一掩模，其中第一掩模包括限定栅电极的第一边缘的开口，去除栅极材料的第一部分以形成由第一掩模限定的栅电极的第一边缘，在去除第一掩模之后在栅极材料上形成第二掩模，其中第二掩模包括限定栅电极的第二边缘的开口，去除第二部分以形成由第二掩模限定的栅电极的第二边缘，并且移除第二掩模。因此，栅电极由第一和第二掩模中的开口之间的横向位移限定。优选地，第一和第二掩模是光致抗蚀剂，并且栅电极的第一和第二边缘之间的长度小于用于对掩模进行图案化的光刻系统的最小分辨率。

7. 发明申请

WO1997041592A1 A FLUORINATED OXIDE LOW PERMITTIVITY DIELECTRIC STACK FOR REDUCED CAPACITIVE COUPLING 审中-公开
标题翻译：用于减少电容耦合的氟化氧化物低电容堆
公开(公告)号：WO1997041592A1
公开(公告)日：1997-11-06
申请号：PCT/US1996020485
申请日：1996-12-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , DAWSON, Robert , HAUSE, Fred, N. , BANDYOPADHYAY, Basab , MICHAEL, Mark, W. , FULFORD, H., Jim , BRENNAN, William, S.
IPC分类号： H01L21/316
CPC分类号： H01L21/76801 , H01L21/76831 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low permittivity interlevel structure comprising a dielectric formed on the topography of a semiconductor substrate. The dielectric comprises a lower region proximal to the semiconductor substrate, an intermediate region comprised of an oxide into which fluorine is incorporated in an atomic concentration of approximately four to ten percent, and an upper region. A method of forming the dielectric structure includes forming a first interconnect level on a substrate. A first dielectric layer, preferably a CVD oxide, is formed on the topography defined by the first interconnect and the substrate. A second dielectric layer, having a dielectric constant lower than the first dielectric layer, is then formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. The second dielectric layer is preferably formed in a CVD chamber from a silane or TEOS source and a fluorinating material such as SiF4.
摘要翻译：包括在半导体衬底的形貌上形成的电介质的低介电常数层间结构。电介质包括靠近半导体衬底的下部区域，由以约4％至10％的原子浓度掺入氟的氧化物构成的中间区域和上部区域。形成电介质结构的方法包括在衬底上形成第一互连电平。在由第一互连和衬底限定的形貌上形成第一电介质层，优选CVD氧化物。然后在第一介电层上形成具有低于第一介电层的介电常数的第二电介质层。在第二电介质层上形成第三电介质层。第二电介质层优选地由硅烷或TEOS源形成在CVD室中，并且氟化材料例如SiF 4。

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