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1. 发明申请

WO1998025182A1 RETICLE THAT COMPENSATES FOR LENS ERROR IN A PHOTOLITHOGRAPHIC SYSTEM 审中-公开
标题翻译：补偿光刻胶系统中的镜头误差的补充
公开(公告)号：WO1998025182A1
公开(公告)日：1998-06-11
申请号：PCT/US1997022616
申请日：1997-12-04
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , MOORE, Bradley, T. , DAWSON, Robert , FULFORD, H., Jim , GARDNER, Mark, I. , HAUSE, Frederick, N. , MICHAEL, Mark, W. , WRISTERS, Derick, J.
IPC分类号： G03F07/20
CPC分类号： G03F7/70433 , G03F1/70 , G03F7/70241
摘要： A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.
摘要翻译：掩模版（130）提供图像图案并补偿光刻系统中的透镜误差。使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。通过调节辐射透射区域（132,134）的配置（或布局），例如通过调节石英基底的顶表面上的铬图案，可以对掩模版进行结构上的修改。或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

2. 发明申请

WO1996031903A1 ADVANCED ISOLATION SCHEME FOR DEEP SUBMICRON TECHNOLOGY 审中-公开
标题翻译：深层潜水技术的先进隔离方案
公开(公告)号：WO1996031903A1
公开(公告)日：1996-10-10
申请号：PCT/US1996002461
申请日：1996-02-23
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , CHANG, Kuang-Yeh , LIU, Yowjuang, William , GARDNER, Mark, I. , HAUSE, Frederick, N.
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76294
摘要： An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.
摘要翻译：氧化物层在半导体本体上热生长，并且在氧化物层中蚀刻开口以暴露半导体主体表面的部分。然后，外延区域从半导体主体生长到氧化物层中的开口中，这些外延区域最终将成为器件的有源区域。

3. 发明申请

WO1998025183A1 INSPECTION OF LENS ERROR ASSOCIATED WITH LENS HEATING IN A PHOTOLITHOGRAPHIC SYSTEM 审中-公开
标题翻译：检查与光学加热系统相关的镜头误差
公开(公告)号：WO1998025183A1
公开(公告)日：1998-06-11
申请号：PCT/US1997023139
申请日：1997-12-04
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , MOORE, Bradley, T. , DAWSON, Robert , FULFORD, H., Jim , GARDNER, Mark, I. , HAUSE, Frederick, N. , MICHAEL, Mark, W. , WRISTERS, Derick, J.
IPC分类号： G03F07/20
CPC分类号： G03F7/70058 , G03F7/70591 , G03F7/70891
摘要： A method of inspecting a lens (16) includes projecting a first amount of radiation through a first test pattern (42, 44) and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern (52, 54) and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.
摘要翻译：检查透镜（16）的方法包括：通过第一测试图案（42,44）和透镜投射第一量的辐射，以提供与透镜的第一加热相关联的第一透镜误差，投射第二量的辐射通过第二测试图案（52,54）和透镜提供与透镜的第二加热相关联的第二透镜误差，并且使用第一和第二透镜误差来提供作为加热透镜的函数而变化的图像位移数据。以这种方式，可以对给定掩模版特有的局部透镜加热进行校正。该方法非常适合于光刻系统，如步进和重复系统。

4. 发明申请

WO1998004892A1 A RAPID THERMAL ANNEAL SYSTEM AND METHOD INCLUDING IMPROVED TEMPERATURE SENSING AND MONITORING 审中-公开
标题翻译：一种快速热绝缘系统和方法，包括改进的温度感测和监测
公开(公告)号：WO1998004892A1
公开(公告)日：1998-02-05
申请号：PCT/US1997005113
申请日：1997-03-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , DAWSON, Robert , HAUSE, Frederick, N. , MAY, Charles, E.
IPC分类号： G01J05/60
CPC分类号： G01J5/601 , G01J5/041 , G01J5/60
摘要： A broadband pyrometer is used for sensing temperature of a semiconductor wafer in an RTA system in association with a monochromator to cancel the backside characteristics of the semiconductor wafer. A rapid thermal anneal (RTA) system includes a rapid thermal anneal (RTA) chamber, a heating lamp arranged in the vicinity of the RTA chamber for heating interior to the RTA chamber, a broadband pyrometer disposed in the vicinity of the RTA chamber and directed to measure interior to the RTA chamber, and a grating monochromator connected to the broadband pyrometer.
摘要翻译：使用宽带高温计来检测与单色仪相关联的RTA系统中的半导体晶片的温度，以消除半导体晶片的背面特性。快速热退火（RTA）系统包括快速热退火（RTA）室，布置在RTA室附近的加热灯，用于加热到RTA室内部，宽带高温计设置在RTA室附近并被引导测量RTA室的内部，以及连接到宽带高温计的光栅单色仪。

5. 发明申请

WO2002075781A2 METHOD OF FORMING SILICIDE CONTACTS AND DEVICE INCORPORATING SAME 审中-公开
标题翻译：形成硅氧烷接触的方法和包含它们的装置
公开(公告)号：WO2002075781A2
公开(公告)日：2002-09-26
申请号：PCT/US2002/002774
申请日：2002-02-01
申请人： ADVANCED MICRO DEVICES, INC.
发明人： PELLERIN, John, G. , CHEEK, Jon, D. , DAWSON, Robert , HAUSE, Frederick, N. , LUNING, Scott, D.
IPC分类号： H01L
CPC分类号： H01L29/66507 , H01L21/823443 , H01L29/665 , H01L29/6653
摘要： A transistor, comprising a semiconducting substrate (30), a gate insulation layer (48) positioned above the substrate (30), agate electrode (46) positioned above the gate insulation layer (48), a plurality of source/drain regions formed in the substrate (30), a first (40A) and a second (52) sidewall spacer positioned adjacent the gate electrode (46), and a metal silicide layer (54) formed above each of the source/drain regions, a portion of the metal silicide layer (54) being positioned adjacent the first sidewall spacer (40A) and under the second sidewall spacer (52). The method comprises forming a transistor by forming a gate insulation layer (48) and a gate electrode (46) above a semiconducting substrate (30), forming a first sidewall spacer (40A) adjacent the gate electrode (46), forming a metal silicide layer (50) adjacent the first sidewall spacer (40A) and above previously formed implant regions in the substrate, forming a second sidewall spacer (52) above a portion of the metal silicide layer (50) and adjacent the first sidewall spacer (40A), and forming additional metal silicide material (50A) above the metal silicide layer (50) extending beyond the second sidewall spacer (52).
摘要翻译：一种晶体管，包括半导体衬底（30），位于衬底（30）上方的栅极绝缘层（48），位于栅极绝缘层（48）上方的玛瑙电极（46），多个源极/漏极区域基板（30），邻近栅电极（46）定位的第一（40A）和第二（52）侧壁间隔物，以及形成在每个源极/漏极区域上方的金属硅化物层（54）金属硅化物层（54）定位成邻近第一侧壁间隔物（40A）并位于第二侧壁间隔物（52）下方。该方法包括通过在半导体衬底（30）上形成栅极绝缘层（48）和栅电极（46）来形成晶体管，形成邻近栅电极（46）的第一侧壁间隔物（40A），形成金属硅化物邻近第一侧壁间隔物（40A）的层（50）以及衬底中先前形成的注入区域，在金属硅化物层（50）的一部分上方并邻近第一侧壁间隔物（40A）形成第二侧壁间隔物（52）并且在金属硅化物层（50）之上形成延伸超过第二侧壁间隔物（52）的附加金属硅化物材料（50A）。

6. 发明申请

WO1998004925A2 STRUCTURE FOR TESTING JUNCTION LEAKAGE OF SALICIDED DEVICES FABRICATED USING SHALLOW TRENCH AND REFILL TECHNIQUES 审中-公开
标题翻译：使用SHOWOW TRENCH和REFILL TECHNIQUES测试破碎设备的结构泄漏结构
公开(公告)号：WO1998004925A2
公开(公告)日：1998-02-05
申请号：PCT/US1997005015
申请日：1997-03-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , HAUSE, Frederick, N. , MAY, Charles, E. , DAWSON, Robert
IPC分类号： G01R00/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.
摘要翻译：在浅沟槽隔离器件结上使用电阻保护罩，以覆盖设备区域外围的条带之外的器件区域。在器件的中心表面部分上形成的硅化物层和在其上防止硅化物形成的器件的周边上的条带区域形成用于评估结合形成的测试结构，其免于在器件沟槽上的硅化物形成的影响侧壁。将测试结构上的电气测试和泄漏测量直接与类似的硅化物浅沟槽隔离器件进行比较，该器件不包含电阻器保护掩膜和没有硅化物的浅沟槽隔离器件，以确定自对准硅化物处理是否包括结漏现象和短路 -circuiting。

7. 发明申请

WO1996031904A1 LIGHTLY DOPED DRAIN PROFILE OPTIMIZATION WITH HIGH ENERGY IMPLANTS 审中-公开
标题翻译：用高能量植入物进行轻型排水剖面优化
公开(公告)号：WO1996031904A1
公开(公告)日：1996-10-10
申请号：PCT/US1996000971
申请日：1996-01-23
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , CHANG, Kuang-Yeh , GARDNER, Mark, I. , HAUSE, Frederick, N.
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/7833
摘要： After growth of a thin oxide on a silicon semiconductor body, and formation of a gate thereover, a blanket layer of oxide is deposited over the resulting structure, this oxide layer having, as measured from the surface of the silicon body, relatively thick regions adjacent the sides of the gate and relatively thin regions extending therefrom. Upon implant of ions, the relatively thick regions block ions from passing therethrough into the semiconductor body, while the relatively thin regions allow passage of ions therethrough into the body. After drivein of the ions, the thick layer of oxide is isotopically etched to take a substantially uniform layer therefrom over the entire surface of the thick oxide layer, so that the thick regions thereof are reduced in width. Upon a subsequent ion implant step, the thick regions, now reduced in width from the sides of the gate, block passage of ions therethrough, while the thin regions allow ions therethrough into the silicon body. This process may be continued as chosen to form desired source and drain profile.
摘要翻译：在硅半导体本体上生长薄氧化物并在其上形成栅极之后，在所得结构上沉积氧化物覆盖层，该氧化物层具有从硅体表面测量的较厚的相邻区域门的侧面和从其延伸的相对薄的区域。在离子注入时，相对较厚的区域阻止离子通过其进入半导体本体，而较薄的区域允许离子通过其进入体内。在离子的驱动之后，厚厚的氧化物层被同位素蚀刻以在厚氧化物层的整个表面上从其中获得基本均匀的层，使得其厚的区域的宽度减小。在随后的离子注入步骤中，现在从栅极的侧面减小宽度的厚区域阻止离子通过其中，而薄区域允许离子通过其进入硅体。该过程可以根据选择继续以形成所需的源极和漏极分布。

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