专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008150005A1 IROX NANOWIRE NEURAL SENSOR 审中-公开
标题翻译： IROX NANOWIRE神经传感器
公开(公告)号：WO2008150005A1
公开(公告)日：2008-12-11
申请号：PCT/JP2008/060509
申请日：2008-06-03
申请人： SHARP KABUSHIKI KAISHA , ZHANG, Fengyan , ULRICH, Bruce, D. , GAO, Wei , HSU, Sheng, Teng
发明人： ZHANG, Fengyan , ULRICH, Bruce, D. , GAO, Wei , HSU, Sheng, Teng
IPC分类号： A61F2/14 , A61F9/007 , A61N1/372 , B82B1/00
CPC分类号： A61N1/0543 , B82Y15/00 , B82Y30/00 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T428/24998
摘要： An iridium oxide (IrOx) nanowire neural sensor array (400) and associated fabrication method are provided. The method provides a substrate (402) with a conductive layer (404) overlying the substrate (402), and a dielectric layer (406) overlying the conductive layer (404). The substrate (402) can be a material such as Si, Siθ2, quartz, glass, or polyimide, and the conductive layer (404) is a material such as ITO, SnO2, ZnO, Tiθ2, doped ITO, doped Snθ2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer (406) is selectively wet etched, forming contact holes (408) with sloped walls in the dielectric layer (406) and exposing regions (412) of the conductive layer (404). IrOx nanowire neural interfaces (414) are grown from the exposed regions (412) of the conductive layer (404). The IrOx nanowire neural interfaces (414) each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.
摘要翻译：提供氧化铱（IrOx）纳米线神经传感器阵列（400）及相关制造方法。该方法提供了具有覆盖在衬底（402）上的导电层（404）的衬底（402）和覆盖在导电层（404）上的电介质层（406）。衬底（402）可以是诸如Si，Si 2，石英，玻璃或聚酰亚胺的材料，并且导电层（404）是诸如ITO，SnO 2，ZnO，Ti 2，掺杂的ITO，掺杂的材料 Sn 2，掺杂的ZnO，掺杂的TiO 2，TiN，TaN，Au，Pt或Ir。电介质层（406）被选择性地被湿蚀刻，形成与电介质层（406）中的倾斜壁和导电层（404）的暴露区域（412）的接触孔（408）。 IrOx纳米线神经接口（414）从导电层（404）的暴露区域（412）生长。 IrOx纳米线神经接口（414）各自具有0.5至10微米的范围的横截面，并且可以被成形为圆形，矩形或椭圆形。

2. 发明申请

WO2008081998A1 MULTIPLE STACKED NANOSTRUCTURE ARRAYS AND METHODS FOR MAKING THE SAME 审中-公开
标题翻译：多层堆叠的纳米结构阵列及其制备方法
公开(公告)号：WO2008081998A1
公开(公告)日：2008-07-10
申请号：PCT/JP2007/075414
申请日：2007-12-27
申请人： SHARP KABUSHIKI KAISHA , ZHANG, Fengyan , HSU, Sheng Teng
发明人： ZHANG, Fengyan , HSU, Sheng Teng
IPC分类号： B82B3/00 , B82B1/00
CPC分类号： H01L29/0665 , B82Y10/00 , G01N27/127 , H01L29/0673 , H01L29/0676 , H01L31/03529 , Y02E10/50
摘要： A method of fabricating a stacked nanostructure array includes preparing a substrate; forming a bottom electrode directly on the substrate; growing a first nanostructure array directly on the bottom electrode; forming an insulating layer on the first nanostructure array; exposing the upper surface of the first nanostructure array; depositing a second, and subsequent, nanostructure array on a nanostructure array immediately below the second and subsequent nanostructure array; repeating said forming, said exposing and said depositing a subsequent steps to form a stacked nanostructure array; removing an uppermost insulating layer; and forming a top electrode on an uppermost nanostructure array. A sensor incorporating the nanostructure array includes top and bottom electrodes with plural layers of nanostructure array therebetween.
摘要翻译：制造叠层纳米结构阵列的方法包括制备基底; 直接在基板上形成底部电极; 直接在底部电极上生长第一个纳米结构阵列; 在第一纳米结构阵列上形成绝缘层; 暴露第一纳米结构阵列的上表面; 在第二和随后的纳米结构阵列正下方的纳米结构阵列上沉积第二和随后的纳米结构阵列; 重复所述形成，所述曝光和沉积随后的步骤以形成堆叠的纳米结构阵列; 去除最上层绝缘层; 并在最上面的纳米结构阵列上形成顶部电极。结合纳米结构阵列的传感器包括其间具有多层纳米结构阵列的顶部和底部电极。

3. 发明申请

WO2008146564A1 NANOROD SENSOR WITH SINGLE-PLANE ELECTRODES 审中-公开
标题翻译： NANOROD传感器与单平面电极
公开(公告)号：WO2008146564A1
公开(公告)日：2008-12-04
申请号：PCT/JP2008/058157
申请日：2008-04-21
申请人： SHARP KABUSHIKI KAISHA , ZHANG, Fengyan , ULRICH, Bruce, D. , PAN, Wei , CHARNESKI, Lawrence, J. , HSU, Sheng, Teng
发明人： ZHANG, Fengyan , ULRICH, Bruce, D. , PAN, Wei , CHARNESKI, Lawrence, J. , HSU, Sheng, Teng
IPC分类号： G01N27/12
CPC分类号： G01N27/127 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/41
摘要： A nanorod sensor with a single plane of horizontally-aligned electrodes and an associated fabrication method are provided. The method provides a substrate and forms an intermediate electrode overlying a center region of the substrate. The intermediate electrode is a patterned bottom noble metal/Pt/Ti multilayered stack. TiO2 nanorods are formed over the substrate and intermediate electrode, and a TiO2 film may be formed overlying the TiO2 nanorods. The TiO2 nanorods and TiO2 film are formed in-situ, in the same process, by varying the substrate temperature. In other aspects, the TiO2 film is formed between the nanorods and the intermediate electrode. In yet another aspect, the TiO2 film is formed both above and below the nanorods. A single plane of top electrodes is formed overlying the TiO2 film from a top noble metal/Pt/Ti multilayered stack overlying the TiO2 film, which has been selectively etched to form separate top electrodes.
摘要翻译：提供了具有水平对准电极的单个平面的纳米棒传感器和相关联的制造方法。该方法提供了一个衬底，并形成了覆盖衬底中心区域的中间电极。中间电极是图案化的底部贵金属/ Pt / Ti多层叠层。在衬底和中间电极上形成TiO 2纳米棒，并且可以在TiO 2纳米棒上形成TiO 2膜。通过改变衬底温度，在相同的工艺中原位形成TiO 2纳米棒和TiO 2膜。在其他方面，在纳米棒和中间电极之间形成TiO 2膜。在另一方面，在纳米棒上方和下方形成TiO 2膜。顶层电极的单面由覆盖在TiO 2膜上的顶部贵金属/ Pt / Ti多层叠层覆盖在TiO 2膜上，该TiO 2膜被选择性地蚀刻以形成分离的顶电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式