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1. 发明申请

WO2004051743A2 RADIATION PROTECTION IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中的辐射防护
公开(公告)号：WO2004051743A2
公开(公告)日：2004-06-17
申请号：PCT/EP0313411
申请日：2003-11-28
申请人： INFINEON TECHNOLOGIES AG , WELLHAUSEN UWE , NAGEL NICOLAS , BRUCHHAUS RAINER , GERNHARDT STEFAN
发明人： WELLHAUSEN UWE , NAGEL NICOLAS , BRUCHHAUS RAINER , GERNHARDT STEFAN
IPC分类号： G06F1/04 , H01L21/02 , H01L23/00 , H01L23/552 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/552 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.
摘要翻译：公开了降低对IC特征的辐射损伤。对辐射敏感的特征的至少一部分被辐射防护层覆盖。辐射防护层在例如IC的处理期间保护特征不被辐射损坏。在一个实施例中，辐射防护层包括贵金属，氧化物，合金或其化合物。

2. 发明申请

WO0120643A3 METHOD FOR PRODUCING A MEMORY, COMPRISING A MEMORY CELL AND A TRENCH ISOLATION 审中-公开
标题翻译：用存储器单元和绝缘沟槽制造存储器的方法
公开(公告)号：WO0120643A3
公开(公告)日：2001-10-04
申请号：PCT/DE0003154
申请日：2000-09-11
申请人： INFINEON TECHNOLOGIES AG , SCHREMS MARTIN , GERNHARDT STEFAN , MORHARD KLAUS DIETER , STEGEMANN MAIK
发明人： SCHREMS MARTIN , GERNHARDT STEFAN , MORHARD KLAUS DIETER , STEGEMANN MAIK
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861
摘要： The invention relates to a method for producing a memory, comprising the following steps: formation of a trench (108) in a substrate (101), formation of an isolation collar (168) in the trench (108), formation of a dielectric layer (164) in the trench (108), filling of the trench (108) with a conductive trench-fill agent (161) and formation of a transistor (110). In order to form a trench isolation (180) once the trench (108) has been filled with the conductive trench-fill agent (161), a trench cover dielectric (430) is also formed in the trench (108) and said trench cover dielectric (430) is used as an etching mask during the formation of the trench isolation (180), in such a way that said trench isolation (180) is formed in a self-aligning manner, in relation to the trench (108). As a result of this self-aligned production of the trench isolation (180), the position of the same (180) is to a great extent independent of the alignment accuracy of the photo-exposure means.
摘要翻译：本发明涉及一种用于制造包括以下步骤的存储器：在衬底中形成（101）的沟槽（108），在沟槽中形成的隔离环（168）（108）在沟槽中形成一个介电层（164）（108），用导电沟槽填充物（161）填充沟槽（108）并形成晶体管（110）。此外，Grabendeckeldielektrikum（430）在沟槽（108）形成，以形成隔离沟槽（180）为一体的形成过程中，沟槽（108）与所述导电严重填充（161）的填充后的隔离沟槽（180）和所述Grabendeckeldielektrikum（430）使用刻蚀掩模，使得隔离沟槽（180）相对于沟槽（108）自对准。由于隔离沟槽（180）的自对准生产，隔离沟槽（180）的位置在很大程度上与光对准器精度无关。

3. 发明申请

WO2004059728A2 METHOD OF FABRICATING AN INTEGRATED CIRCUIT HAVING REDUCED STRESS AND SEMICONDUCTOR CHIP 审中-公开
标题翻译：制造具有降低应力和半导体芯片的集成电路的方法
公开(公告)号：WO2004059728A2
公开(公告)日：2004-07-15
申请号：PCT/EP0314415
申请日：2003-12-17
申请人： INFINEON TECHNOLOGIES AG
发明人： BRUCHHAUS RAINER , GERNHARDT STEFAN , HILLIGER ANDREAS , LIAN JINGYU , NAGEL NICOLAS , WELLHAUSEN UWE
IPC分类号： H01L21/8246 , H01L23/00 , H01L21/02 , H01L21/8239 , H01L27/105
CPC分类号： H01L27/11502 , H01L23/562 , H01L27/11507 , H01L27/1159 , H01L29/7842 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.
摘要翻译：为了减少弯曲，半导体芯片减小了对基板上的有效应力的应力。为了降低有效应力，在芯片的背面设置应力补偿层。应力补偿层产生与IC产生的应力相反的应力。因此，降低了基板上的整体或有效应力。

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