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1. 发明申请

WO2009145979A2 EFFICIENT VEHICLE POWER SYSTEMS 审中-公开
标题翻译：高效的车辆动力系统
公开(公告)号：WO2009145979A2
公开(公告)日：2009-12-03
申请号：PCT/US2009038082
申请日：2009-03-24
申请人： MCCLANAHAN ROBERT F , WASHBURN ROBERT D
发明人： MCCLANAHAN ROBERT F , WASHBURN ROBERT D
IPC分类号： F02B73/00 , F02D25/00 , F02D41/04 , F02D45/00
CPC分类号： B60K5/08
摘要： The present disclosure teaches a fuel efficient method for powering a vehicle. The total peak power requirements for a moving vehicle under a set of performance criteria are divided into at least two subgroups. A primary engine is provided with a size and output to provide for the peak power for one of the at least two subgroups and one or more auxiliary engines or auxiliary engine subsystems are provided with a size and output to provide for up to the peak power for the remaining one or more subgroups.
摘要翻译：本公开教导了一种用于为车辆供电的燃料效率方法。在一组性能标准下的移动车辆的总峰值功率要求被划分为至少两个子组。主发动机具有尺寸和输出以提供至少两个子组中的一个的峰值功率，并且一个或多个辅助发动机或辅助发动机子系统具有尺寸和输出以提供高达峰值功率剩余的一个或多个子组。

2. 发明申请

WO2006026171A3 ENHANCED TIMING MARGIN MEMORY INTERFACE 审中-公开
标题翻译：增强时序存储界面
公开(公告)号：WO2006026171A3
公开(公告)日：2007-08-02
申请号：PCT/US2005029328
申请日：2005-08-17
申请人： THUNDER CREATIVE TECHNOLOGIES , WASHBURN ROBERT D , MCCLANAHAN ROBERT F
发明人： WASHBURN ROBERT D , MCCLANAHAN ROBERT F
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C5/04 , G11C7/10 , G11C7/1048 , G11C7/1051 , G11C7/1066
摘要： The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.
摘要翻译：本发明是一种显着增强高速数字存储器模块中的定时裕度的电子电路。电路实现适用于驱动存储器总线的控制和数据信号线上的所有开关波形。本发明的实现还提供了与利用本技术相当的尺寸和速度的存储器模块相比，功率耗散的显着降低。

3. 发明申请

WO2007056730A2 VARIABLE PASSIVE COMPONENTS WITH HIGH RESOLUTION VALUE SELECTION AND CONTROL 审中-公开
标题翻译：具有高分辨率选择和控制的可变被动组件
公开(公告)号：WO2007056730A2
公开(公告)日：2007-05-18
申请号：PCT/US2006/060622
申请日：2006-11-07
申请人： THUNDER CREATIVE TECHNOLOGIES, INC. , WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
发明人： WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
IPC分类号： H03K17/16
CPC分类号： H03H7/25 , H03F1/08 , H03F1/3211 , H03F1/56 , H03F3/343 , H03F3/4508 , H03F3/45475 , H03F2200/222 , H03F2200/321 , H03F2200/387 , H03F2200/91 , H03F2203/45031 , H03F2203/45136 , H03F2203/45352 , H03H7/40 , H03H11/30 , H03H11/48 , H03H11/481 , H03H11/53
摘要： The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.
摘要翻译：本系统提供了一种改变电子电路中无源元件的值的方法。无源元件可以从基本的电阻器，电容器和电感器到复杂的结构，如传输线和谐振腔。价值选择和变化可以在电路运行期间动态执行，也可以作为制造过程的一次性部分，由特定应用的要求确定。数模转换器（DAC）电路用于数字输入值选择数据，并根据DAC的分辨率根据值分辨率进行控制值选择。提供了用于高频操作的替代实施例。

4. 发明申请

WO2005025064A2 COMMON MODE TRANSMISSION LINE TERMINATION 审中-公开
标题翻译：共通模式传输线终止
公开(公告)号：WO2005025064A2
公开(公告)日：2005-03-17
申请号：PCT/US2004/029061
申请日：2004-09-03
申请人： THUNDER CREATIVE TECHNOLOGIES, INC. , WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
发明人： WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
IPC分类号： H03K
CPC分类号： H04L25/0298
摘要： The present invention provides termination for transmission line structures propagating common mode signals. Common mode signals typically represent noise in systems wherein information is transmitted as differential mode signals. The present invention terminates the common mode signals in a dynamically matched termination that prevents or significantly reduces reflection of said common signals without interference with differential mode transmission lines or their normal operation. Application is shown for an unshielded, twisted pair transmission line as commonly used in telephony-based systems for both voice and broadband data communication. The methods for application of the present invention to systems with large numbers of conductors are also shown.
摘要翻译：本发明提供了传播共模信号的传输线结构的终止。共模信号通常表示系统中的噪声，其中信息作为差模信号被发送。本发明在动态匹配的终端中终止共模信号，防止或显着减少所述公共信号的反射，而不会干扰差模传输线或其正常操作。显示了用于语音和宽带数据通信的基于电话的系统中通常使用的非屏蔽双绞线传输线的应用。还示出了将本发明应用于具有大量导体的系统的方法。

5. 发明申请

WO2006127959A3 CONTROL SIGNAL INTERFACE CIRCUIT FOR COMPUTER MEMORY MODULES 审中-公开
标题翻译：用于计算机存储器模块的控制信号接口电路
公开(公告)号：WO2006127959A3
公开(公告)日：2007-07-26
申请号：PCT/US2006020353
申请日：2006-05-25
申请人： THUNDER CREATIVE TECHNOLOGIES , WASHBURN ROBERT D , MCCLANAHAN ROBERT F
发明人： WASHBURN ROBERT D , MCCLANAHAN ROBERT F
IPC分类号： G11C5/14
CPC分类号： G11C5/04
摘要： The invention is an electronic circuit designed for incorporation on computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.
摘要翻译：本发明是一种设计用于并入诸如DDR DIMM的计算机存储器模块上的电子电路。它在模块输入连接器和存储器件之间耦合控制信号，如地址位，存储区选择，使能和偶数时钟信号。该电路提供低传播延迟，快速上升和下降时间，没有过冲或下冲，并且与现有技术的存储器模块相比，显着地提高了时序控制。主板上的电容负载通常远小于单个存储器件输入提供的负载，并且与每个存储器的存储器件数量或存储器模块上存储器件组的数量无关。对于连接到存储器总线的多个存储器模块，容性负载基本上是单个存储器模块的等效负载的N倍。

6. 发明申请

WO2006127959A2 CONTROL SIGNAL INTERFACE CIRCUIT FOR COMPUTER MEMORY MODULES 审中-公开
标题翻译：用于计算机存储器模块的控制信号接口电路
公开(公告)号：WO2006127959A2
公开(公告)日：2006-11-30
申请号：PCT/US2006/020353
申请日：2006-05-25
申请人： THUNDER CREATIVE TECHNOLOGIES, INC. , WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
发明人： WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
IPC分类号： G11C5/14
CPC分类号： G11C5/04
摘要： The invention is an electronic circuit designed for incorporation on computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.
摘要翻译：本发明是一种设计用于并入诸如DDR DIMM的计算机存储器模块上的电子电路。它在模块输入连接器和存储器件之间耦合控制信号，如地址位，存储区选择，使能和偶数时钟信号。该电路提供低传播延迟，快速上升和下降时间，没有过冲或下冲，并且与现有技术的存储器模块相比，显着地提高了时序控制。主板上的电容负载通常远小于单个存储器件输入提供的负载，并且与每个存储体的存储器件数量或存储器模块上存储器件组的数量无关。对于连接到存储器总线的多个存储器模块，容性负载基本上是单个存储器模块的等效负载的N倍。

7. 发明申请

WO2004114576A2 SYSTEM FOR CROSSTALK NOISE REDUCTION ON TWISTED PAIR, ETHERNET, POLYPHASE AND SHIELDED WIRE SYSTEMS 审中-公开
标题翻译：双绞线，以太网，多晶和屏蔽线系统中的摇摆噪声减少系统
公开(公告)号：WO2004114576A2
公开(公告)日：2004-12-29
申请号：PCT/US2004/019501
申请日：2004-06-18
申请人： THUNDER CREATIVE TECHNOLOGIES, INC. , WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
发明人： WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
IPC分类号： H04L
CPC分类号： H04M3/34 , H04B3/32 , H04M3/304
摘要： The present invention is an electronic circuit that reduces crosstalk in communications systems employing twisted pair, Ethernet, polyphase or shielded wire transmission media. The present invention includes three stages of crosstalk noise reduction. Stage 1 filters common mode noise from the transmission media and balances the resistive and reactive parasitic electrical characteristics of the transmission media that couple each line to the local ground over the operating frequency band. The second Stage performs differential crosstalk noise reduction in real time using multiple feedback loops. It can dynamically locate and set optimal system operating conditions for minimal differential crosstalk coupling for the specific environmental and interfering channel utilization conditions. The third Stage utilizes digital signal processing techniques to further reduce any residual crosstalk after analog-to-digital conversion. The third Stage also functions as a digital controller for the entire system as well as portions fo subsystems including the feedback loops of Stage 2.

8. 发明申请

WO2007056730A3 VARIABLE PASSIVE COMPONENTS WITH HIGH RESOLUTION VALUE SELECTION AND CONTROL 审中-公开
标题翻译：具有高分辨率选择和控制的可变被动组件
公开(公告)号：WO2007056730A3
公开(公告)日：2008-07-17
申请号：PCT/US2006060622
申请日：2006-11-07
申请人： WASHBURN ROBERT D , MCCLANAHAN ROBERT F
发明人： WASHBURN ROBERT D , MCCLANAHAN ROBERT F
IPC分类号： H03M1/66
CPC分类号： H03H7/25 , H03F1/08 , H03F1/3211 , H03F1/56 , H03F3/343 , H03F3/4508 , H03F3/45475 , H03F2200/222 , H03F2200/321 , H03F2200/387 , H03F2200/91 , H03F2203/45031 , H03F2203/45136 , H03F2203/45352 , H03H7/40 , H03H11/30 , H03H11/48 , H03H11/481 , H03H11/53
摘要： The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.
摘要翻译：本系统提供了一种改变电子电路中无源元件的值的方法。无源元件可以从基本的电阻器，电容器和电感器到复杂的结构，如传输线和谐振腔。价值选择和变化可以在电路运行期间动态执行，也可以作为制造过程的一次性部分，由特定应用的要求确定。数模转换器（DAC）电路用于数字输入值选择数据，并根据DAC的分辨率根据值分辨率进行控制值选择。提供了用于高频操作的替代实施例。

9. 发明申请

WO2006128049A3 TRANSFORMER COUPLED CLOCK INTERFACE CIRCUIT FOR MEMORY MODULES 审中-公开
标题翻译：用于存储器模块的变压器耦合时钟接口电路
公开(公告)号：WO2006128049A3
公开(公告)日：2007-07-12
申请号：PCT/US2006020597
申请日：2006-05-25
申请人： THUNDER CREATIVE TECHNOLOGIES , WASHBURN ROBERT D , MCCLANAHAN ROBERT F
发明人： WASHBURN ROBERT D , MCCLANAHAN ROBERT F
IPC分类号： G11C5/14
CPC分类号： G11C5/04
摘要： The invention is a clock interface circuit for high-speed computer memory modules. It provides improved timing margin due to improved rise and fall times than achieved with present JEDEC specified clock distribution and timing networks. The invention also provides for improved clock and inverse clock symmetry around VREF.
摘要翻译：本发明是用于高速计算机存储器模块的时钟接口电路。由于改进的上升和下降时间，与目前JEDEC规定的时钟分配和定时网络相比，提供了改进的时序裕度。本发明还提供围绕VREF的改进的时钟和逆时钟对称性。

10. 发明申请

WO2006128049A2 TRANSFORMER COUPLED CLOCK INTERFACE CIRCUIT FOR MEMORY MODULES 审中-公开
标题翻译：用于存储器模块的变压器耦合时钟接口电路
公开(公告)号：WO2006128049A2
公开(公告)日：2006-11-30
申请号：PCT/US2006/020597
申请日：2006-05-25
申请人： THUNDER CREATIVE TECHNOLOGIES, INC. , WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
发明人： WASHBURN, Robert, D. , MCCLANAHAN, Robert, F.
IPC分类号： G11C5/14
CPC分类号： G11C5/04
摘要： The invention is a clock interface circuit for high-speed computer memory modules. It provides improved timing margin due to improved rise and fall times than achieved with present JEDEC specified clock distribution and timing networks. The invention also provides for improved clock and inverse clock symmetry around VREF.
摘要翻译：本发明是用于高速计算机存储器模块的时钟接口电路。由于改进的上升和下降时间，与目前JEDEC规定的时钟分配和定时网络相比，提供了改进的时序裕度。本发明还提供围绕VREF的改进的时钟和逆时钟对称性。

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