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    • 1. 发明申请
    • VDMOS DEVICE AND METHOD FOR FABRICATING THE SAME
    • VDMOS器件及其制造方法
    • WO2012065515A1
    • 2012-05-24
    • PCT/CN2011/081743
    • 2011-11-03
    • CSMC TECHNOLOGIES FAB1 CO., LTDCSMC TECHNOLOGIES FAB2 CO., LTD.WANG, Le
    • WANG, Le
    • H01L29/78H01L21/336
    • H01L29/7802H01L21/26533H01L29/0653H01L29/0878H01L29/66719
    • A Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device and a method for fabricating the same are provided. The VDMOS device includes a substrate which includes a body layer (201) and an epitaxial layer (202) formed over the body layer (201). The body layer (201) has a drain region. The VDMOS device further includes an isolating region (203) formed in the epitaxial layer (202), a first body region (204) and a second body region (205) formed in the epitaxial layer (202) and located at two sides of the isolating region (203), a first source region (206) and a second source region (207) formed in the first body region (204) and the second body region (205) respectively, and a gate region formed above the isolating region (203) and located between the first source region (206) and the second source region (207).
    • 提供了垂直双扩散金属氧化物半导体(VDMOS)器件及其制造方法。 VDMOS器件包括衬底,其包括主体层(201)和形成在体层(201)上的外延层(202)。 主体层(201)具有漏极区域。 VDMOS器件还包括形成在外延层(202)中的隔离区(203),形成在外延层(202)中的第一体区(204)和第二体区(205) 隔离区域(203),分别形成在第一体区(204)和第二体区(205)中的第一源极区(206)和第二源极区(207),以及形成在隔离区 203)并且位于第一源极区(206)和第二源极区(207)之间。
    • 2. 发明申请
    • LDMOS DEVICE AND METHOD FOR FABRICATING THE SAME
    • LDMOS器件及其制造方法
    • WO2012065485A1
    • 2012-05-24
    • PCT/CN2011/080671
    • 2011-10-12
    • CSMC TECHNOLOGIES FAB1 CO., LTD.CSMC TECHNOLOGIES FAB2 CO., LTD.WANG, Le
    • WANG, Le
    • H01L29/78H01L21/336
    • H01L29/7816H01L29/0634H01L29/0696H01L29/0878H01L29/42368
    • An LDMOS device and a method for fabricating the same are disclosed in embodiments of the present invention. The device includes: a substrate including an epitaxial layer and a well region located in a surface of the epitaxial layer; a source region located in the well region, and a drain region located in the epitaxial layer; a first region and a second region located in the surface of the epitaxial layer and having doping states different from a doping state of the epitaxial layer, where the first region and the second region are located in a drift region between the source region and the drain region, and have different doping states; a field oxide layer located above the first region and the second region; and a gate region located on the well region and the field oxide layer. In the present invention, by replacing the drift region with only one doping state in the prior art with the first region and the second region having different doping states, the doping states of the first region and the second region can be adjusted according to the requirements for the breakdown voltage and the on-resistance, so that the on-resistance is further decreased and the power consumption of the device is reduced while a high breakdown voltage is ensured.
    • 在本发明的实施例中公开了一种LDMOS器件及其制造方法。 该器件包括:衬底,其包括位于外延层的表面中的外延层和阱区; 位于阱区中的源极区和位于外延层中的漏极区; 位于所述外延层的表面中的第一区域和第二区域,并且具有不同于所述外延层的掺杂状态的掺杂态,其中所述第一区域和所述第二区域位于所述源极区域和所述漏极之间的漂移区域中 并具有不同的掺杂态; 位于所述第一区域和所述第二区域上方的场氧化物层; 以及位于阱区和场氧化物层上的栅极区。 在本发明中,通过在现有技术中仅利用一种掺杂状态代替漂移区域,第一区域和第二区域具有不同的掺杂态,可以根据需要调整第一区域和第二区域的掺杂状态 对于击穿电压和导通电阻,导通电阻进一步降低,并且在确保高击穿电压的同时降低器件的功耗。
    • 3. 发明申请
    • METHOD FOR FABRICATING SMALL-SCALE MOS DEVICE
    • 用于制作小尺寸MOS器件的方法
    • WO2012048624A1
    • 2012-04-19
    • PCT/CN2011/080557
    • 2011-10-09
    • CSMC TECHNOLOGIES FAB1 CO.,LTD.CSMC TECHNOLOGIES FAB2 CO.,LTD.WANG, Le
    • WANG, Le
    • H01L21/336H01L21/265
    • H01L29/66492H01L29/665H01L29/6659H01L29/66636H01L29/7833
    • A method for fabricating a small-scale MOS device, including: preparing a substrate; forming a first trench in the substrate along a first side of the gate region and forming a second trench in the substrate along a second side of the gate region, the first side of the gate region opposite the second side of the gate region; forming a first lightly doped drain region and a second lightly doped drain region in the first trench and the second trench, respectively; forming a third trench in the substrate overlapping at least a first portion of the first lightly doped drain region and a fourth trench in the substrate overlapping at least a first portion of the second lightly doped drain region; and forming a source region and a drain region in the third trench and the fourth trench, respectively.
    • 一种制造小型MOS器件的方法,包括:制备衬底; 在所述栅极区域的第一侧沿所述衬底中形成第一沟槽,并沿所述栅极区域的第二侧在所述衬底中形成第二沟槽,所述栅极区域与所述栅极区域的第二侧相对的第一侧; 在第一沟槽和第二沟槽中分别形成第一轻掺杂漏极区和第二轻掺杂漏极区; 在所述衬底中形成与所述第一轻掺杂漏极区的至少第一部分重叠的第三沟槽,并且所述衬底中的第四沟槽与所述第二轻掺杂漏极区的至少第一部分重叠; 以及在第三沟槽和第四沟槽中分别形成源区和漏区。
    • 4. 发明申请
    • MOS DEVICE AND FABRICATING METHOD THEREOF
    • MOS器件及其制造方法
    • WO2012031546A1
    • 2012-03-15
    • PCT/CN2011/079359
    • 2011-09-06
    • CSMC TECHNOLOGIES FAB1 CO., LTDCSMC TECHNOLOGIES FAB2 CO., LTD.WANG, Le
    • WANG, Le
    • H01L21/336H01L29/78H01L21/20H01L21/22
    • H01L29/66651
    • AMOS device and a fabricating method thereof are provided. The fabricating method of the MOS device includes the steps of growing an implanted oxide layer on a substrate (11), forming a well (13) in the substrate (11) by lithography and an ion implantation process, removing the implanted oxide layer, then depositing an epitaxial layer (15) on the surface of the substrate (11) to form a channel region, growing a gate oxide (17) on the epitaxial layer (15), depositing a poly-silicon layer on the gate oxide (17), and then etching the poly-silicon layer to form a gate (19), and implanting ions into the epitaxial layer (15) and the well (13) to form a source (21) and a drain (23) on opposite lateral sides of the gate (19). By using a deposition process to form the epitaxial layer for the channel region, the doping concentration and thickness of the channel region are uniform, and the threshold voltage is stable.
    • 提供AMOS器件及其制造方法。 MOS器件的制造方法包括以下步骤:在衬底(11)上生长注入的氧化物层,通过光刻和离子注入工艺在衬底(11)中形成阱(13),去除注入的氧化物层,然后 在所述衬底(11)的表面上沉积外延层(15)以形成沟道区域,在所述外延层(15)上生长栅极氧化物(17),在所述栅极氧化物(17)上沉积多晶硅层 ,然后蚀刻多晶硅层以形成栅极(19),并且将离子注入到外延层(15)和阱(13)中,以在相对的侧面上形成源极(21)和漏极(23) 的门(19)。 通过使用沉积工艺形成用于沟道区的外延层,沟道区的掺杂浓度和厚度是均匀的,并且阈值电压是稳定的。