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1. 发明申请

WO2007095080A8 MEMORY CIRCUIT SYSTEM AND METHOD 审中-公开
标题翻译：存储器电路系统和方法
公开(公告)号：WO2007095080A8
公开(公告)日：2008-05-22
申请号：PCT/US2007003460
申请日：2007-02-08
申请人： RAJAN SURESH NATARAJAN , SMITH MICHAEL JOHN SEBASTIAN , SCHAKEL KEITH R , WANG DAVID T , WEBER FREDERICK DANIEL
发明人： RAJAN SURESH NATARAJAN , SMITH MICHAEL JOHN SEBASTIAN , SCHAKEL KEITH R , WANG DAVID T , WEBER FREDERICK DANIEL
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. In another embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits. In yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, a buffer circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, an interface circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system so to operate the memory stack as a single DRAM integrated circuit.
摘要翻译：提供了一种存储器电路系统和方法。在一个实施例中，接口电路能够与多个存储器电路和系统通信。在使用中，接口电路可操作以连接存储器电路和系统，以减少存储器电路的命令调度约束。在另一个实施例中，接口电路能够与多个存储器电路和系统通信。在使用中，接口电路可操作地转换与在系统和存储器电路之间传送的命令相关联的地址。在另一个实施例中，至少一个存储器堆叠包括多个DRAM集成电路。此外，耦合到主机系统的缓冲电路用于将存储器堆栈与主机系统进行接口，以便在DRAM集成电路和主机系统之间变换一个或多个物理参数。在又一实施例中，至少一个存储器堆叠包括多个DRAM集成电路。此外，耦合到主机系统的接口电路用于将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。

2. 发明申请

WO2010144624A1 PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES 审中-公开
标题翻译： DIMM终止电阻值的编程
公开(公告)号：WO2010144624A1
公开(公告)日：2010-12-16
申请号：PCT/US2010/038041
申请日：2010-06-09
申请人： GOOGLE INC. , FEROLITO, Philip Arnold , ROSENBAND, Daniel L. , WANG, David T. , SMITH, Michael John Sebastian
发明人： FEROLITO, Philip Arnold , ROSENBAND, Daniel L. , WANG, David T. , SMITH, Michael John Sebastian
IPC分类号： G06F13/40
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
摘要翻译：提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。

3. 发明申请

WO2008063251A3 MEMORY CIRCUIT SYSTEM AND METHOD 审中-公开
标题翻译：存储器电路系统和方法
公开(公告)号：WO2008063251A3
公开(公告)日：2008-10-16
申请号：PCT/US2007016385
申请日：2007-07-18
申请人： METARAM INC , RAJAN SURESH NATARAJAN , SCHAKEL KEITH R , SMITH MICHAEL JOHN SEBASTIAN , WANG DAVID T , WEBER FREDERICK DANIEL
发明人： RAJAN SURESH NATARAJAN , SCHAKEL KEITH R , SMITH MICHAEL JOHN SEBASTIAN , WANG DAVID T , WEBER FREDERICK DANIEL
IPC分类号： G06F9/455 , G06F1/00 , G06F12/00
CPC分类号： G11C5/04 , G06F1/3225 , G06F2213/0038 , G11C5/06 , G11C5/14 , G11C8/12 , G11C11/4074 , G11C2211/4067
摘要： A memory circuit system (Figure 1) and method are provided in the context of various embodiments. In one embodiment, an interface circuit (102) remains in communication with a plurality of memory circuits (104) and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
摘要翻译：在各种实施例的上下文中提供了存储器电路系统（图1）和方法。在一个实施例中，接口电路（102）保持与多个存储器电路（104）和系统通信。接口电路可操作以将存储器电路和系统接口用于执行各种功能（例如电源管理，仿真/仿真等）。

4. 发明申请

WO2007095080A3 MEMORY CIRCUIT SYSTEM AND METHOD 审中-公开
标题翻译：存储器电路系统和方法
公开(公告)号：WO2007095080A3
公开(公告)日：2008-04-10
申请号：PCT/US2007003460
申请日：2007-02-08
申请人： RAJAN SURESH NATARAJAN , SMITH MICHAEL JOHN SEBASTIAN , SCHAKEL KEITH R , WANG DAVID T , WEBER FREDERICK DANIEL
发明人： RAJAN SURESH NATARAJAN , SMITH MICHAEL JOHN SEBASTIAN , SCHAKEL KEITH R , WANG DAVID T , WEBER FREDERICK DANIEL
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. In another embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits. In yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, a buffer circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, an interface circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system so to operate the memory stack as a single DRAM integrated circuit.
摘要翻译：存储器电路系统和方法被提供。在一个实施例中，接口电路能够与多个存储器电路和系统通信。在使用中，接口电路可操作以连接存储器电路和系统以减少存储器电路的命令调度约束。在另一个实施例中，接口电路能够与多个存储器电路和系统通信。在使用中，接口电路可操作以转换与在系统和存储器电路之间传送的命令相关联的地址。在又一个实施例中，至少一个存储器堆叠包括多个DRAM集成电路。此外，耦合到主机系统的缓冲器电路被用于将存储器堆栈连接到主机系统，用于在DRAM集成电路和主机系统之间转换一个或多个物理参数。在又一个实施例中，至少一个存储器堆叠包括多个DRAM集成电路。此外，耦合到主机系统的接口电路用于将存储器堆栈连接到主机系统，以便将存储器堆栈作为单个DRAM集成电路来操作。

5. 发明申请

WO2009026420A1 SYSTEM AND METHOD FOR REDUCING AIR BUBBLES IN A FLUID DELIVERY LINE 审中-公开
标题翻译：用于减少流体输送管线中的空气泡沫的系统和方法
公开(公告)号：WO2009026420A1
公开(公告)日：2009-02-26
申请号：PCT/US2008/073828
申请日：2008-08-21
申请人： HOSPIRA, INC. , WANG, David, T. , COUSINEAU, Robert, P. , LUCKE, Lori, E. , FATHALLAH, Marwan, A. , ZIEGLER, John, S.
发明人： WANG, David, T. , COUSINEAU, Robert, P. , LUCKE, Lori, E. , FATHALLAH, Marwan, A. , ZIEGLER, John, S.
IPC分类号： A61M1/00
CPC分类号： A61M5/16831 , A61M5/365 , G06F19/00
摘要： A method and pump that accurately senses air in a fluid delivery line pulses or activates and deactivates the air sensor(s) multiple times during the pumping phase of the fluid delivery cycle and can generate alarms based upon a single indication or a cumulative indication of air in the line. The pump can include multiple air sensors spaced along the delivery line so that the method can use the multiple signals therefrom to distinguish real moving air bubbles from false positives and/or air bubbles adhered to the inner wall of the line.
摘要翻译：精确地感测流体输送管线中的空气的方法和泵在流体输送循环的泵送阶段期间脉冲或激活和停用空气传感器多次，并且可以基于空气的单一指示或累积指示产生报警在线泵可以包括沿着输送管线间隔开的多个空气传感器，使得该方法可以使用其中的多个信号来区分真实移动的气泡与粘附到管线的内壁上的假阳性和/或气泡区分开。

6. 发明申请

WO2008063251A2 MEMORY CIRCUIT SYSTEM AND METHOD 审中-公开
标题翻译：存储器电路系统和方法
公开(公告)号：WO2008063251A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/016385
申请日：2007-07-18
申请人： METARAM, INC. , RAJAN, Suresh Natarajan , SCHAKEL, Keith, R. , SMITH, Michael John Sebastian , WANG, David, T. , WEBER, Frederick Daniel
发明人： RAJAN, Suresh Natarajan , SCHAKEL, Keith, R. , SMITH, Michael John Sebastian , WANG, David, T. , WEBER, Frederick Daniel
IPC分类号： G11C5/14
CPC分类号： G11C5/04 , G06F1/3225 , G06F2213/0038 , G11C5/06 , G11C5/148 , G11C8/12 , G11C11/4074 , G11C2211/4067
摘要： A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
摘要翻译：在各种实施例的上下文中提供存储器电路系统和方法。在一个实施例中，接口电路保持与多个存储器电路和系统通信。接口电路可操作以将存储器电路和系统接口用于执行各种功能（例如电源管理，仿真/仿真等）。

7. 发明申请

WO2008024908A2 SYSTEM AND METHOD FOR IMPROVED LOW FLOW MEDICAL PUMP DELIVERY 审中-公开
标题翻译：用于改善低流量医疗泵递送的系统和方法
公开(公告)号：WO2008024908A2
公开(公告)日：2008-02-28
申请号：PCT/US2007/076636
申请日：2007-08-23
申请人： HOSPIRA, INC. , WANG, David, T. , SCARAMUZZI, Peter, J. , SALEKI, Mansour, A. , COUSINEAU, Robert, P. , ABRAHAMSON, Kent, D. , LAWLESS, Michael, W. , FATHALLAH, Marwan, A. , KIDD, Brian, A. , BOYD, Robert, R. , GREENE, Howard, L. , NAVIN, Eric, R. , LUCKE, Lori, E. , MULLIN, Benjamin, T.
发明人： WANG, David, T. , SCARAMUZZI, Peter, J. , SALEKI, Mansour, A. , COUSINEAU, Robert, P. , ABRAHAMSON, Kent, D. , LAWLESS, Michael, W. , FATHALLAH, Marwan, A. , KIDD, Brian, A. , BOYD, Robert, R. , GREENE, Howard, L. , NAVIN, Eric, R. , LUCKE, Lori, E. , MULLIN, Benjamin, T.
IPC分类号： G11C13/00
CPC分类号： A61M5/14224 , A61M5/16809 , A61M5/16854 , A61M5/172 , A61M2205/128 , A61M2205/3331
摘要： A medical pump with an improved continuity low flow delivery system and method for use with a pumping chamber, for example in a cassette, is disclosed. The pump includes a pump drive for exerting a force on the pumping chamber and a sensor for sensing the force/pressure exerted by the pump drive on the pumping chamber. The pump drive position sensor senses the position of the pump drive. The medical pump also includes a processing unit and a memory having a programming code adapted to calculate the rate of change of the sensed force/pressure values and determine whether the rate of change of the sensed force/pressure values meets a rate of change threshold. Once the rate of change threshold is met, the programming code is adapted to calculate a remaining pump drive travel value for determining how much farther the pump drive should travel before the end of an effective pump cycle. The programming code is further adapted to trigger one or more signals to drive the pump drive for the remainder of the effective pump cycle using the remaining pump drive travel value.
摘要翻译：公开了一种具有改进的连续性低流量输送系统的医疗泵以及用于例如在盒中的泵送室的方法。该泵包括用于在泵送室上施加力的泵驱动器和用于检测由泵驱动器施加在泵送室上的力/压力的传感器。泵驱动位置传感器检测泵驱动的位置。医疗泵还包括处理单元和具有编程代码的存储器，所述编程代码适于计算感测的力/压力值的变化率并确定感测的力/压力值的变化率是否满足变化率阈值。一旦满足变化率阈值，编程代码适于计算剩余的泵驱动行程值，以确定在有效泵循环结束之前泵驱动应该行进多远。编程代码进一步适用于使用剩余泵驱动行程值触发一个或多个信号以驱动泵驱动器进行剩余的有效泵循环。

8. 发明申请

WO1983001521A1 A PAGE MODIFICATION METHOD IN A PRINTER SUBSYSTEM OF THE PARTIAL PAGE BUFFER COMPOSING TYPE 审中-公开
标题翻译：部分页面缓冲器组合类型的打印机子系统中的页面修改方法
公开(公告)号：WO1983001521A1
公开(公告)日：1983-04-28
申请号：PCT/US1981001380
申请日：1981-10-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DISBROW, John, R. , EISELEN, Everett, T. , FINDLEY, Gerald, I. , LUNING, Stephen, G. , WANG, David, T.
发明人： INTERNATIONAL BUSINESS MACHINES CORPORATION
IPC分类号： G06F03/12
CPC分类号： G01C21/28 , G01C22/02 , G01C22/025 , G06F3/1295 , G06F3/1297 , G06K15/00 , G06K2215/0088
摘要： A page (BASE PAGE) modification method in a printer subsystem of the partial page buffer composing type for generation of distinct copy groups (CG #1, CG #2, CG #3) or versions of a base page. A printer subsystem receives a packet containing a page of characters, coded overlays/elisions (OL #1, OL #2, S #1, S #2) and combining data from an external source. The packet is translated into a linked list of character placement representations for each of the doubly indexed coded characters within the page. Elisions (S #1, S #2) from the page are made by inhibiting the formation of a linked list segment for each character sequence within elision markers set out in the page. In contrast, coded character overlays are appended to the list as addenda. The list governs the placement of characters into a partial page buffer, whose contents are system accessible in row major order.
摘要翻译：用于生成不同复制组（CG＃1，CG＃2，CG＃3）的部分页面缓冲区组合类型的打印机子系统中的页面（BASE PAGE）修改方法或基本页面的版本。打印机子系统接收包含字符页面，编码覆盖/分割（OL＃1，OL＃2，S＃1，S＃2）并组合来自外部源的数据的分组。该分组被翻译成页面内的每个双重索引的编码字符的字符布置表示的链接列表。通过禁止在页面中设置的精确标记内的每个字符序列形成链接列表段来进行页面中的错误（S＃1，S＃2）。相比之下，编码字符叠加作为附录附加到列表中。列表管理字符放置到部分页面缓冲区中，其内容可以按行主顺序访问。

9. 发明申请

WO2008024908A3 SYSTEM AND METHOD FOR IMPROVED LOW FLOW MEDICAL PUMP DELIVERY 审中-公开
标题翻译：改进的低流量医用泵输送系统和方法
公开(公告)号：WO2008024908A3
公开(公告)日：2008-11-20
申请号：PCT/US2007076636
申请日：2007-08-23
申请人： HOSPIRA INC , WANG DAVID T , SCARAMUZZI PETER J , SALEKI MANSOUR A , COUSINEAU ROBERT P , ABRAHAMSON KENT D , LAWLESS MICHAEL W , FATHALLAH MARWAN A , KIDD BRIAN A , BOYD ROBERT R , GREENE HOWARD L , NAVIN ERIC R , LUCKE LORI E , MULLIN BENJAMIN T
发明人： WANG DAVID T , SCARAMUZZI PETER J , SALEKI MANSOUR A , COUSINEAU ROBERT P , ABRAHAMSON KENT D , LAWLESS MICHAEL W , FATHALLAH MARWAN A , KIDD BRIAN A , BOYD ROBERT R , GREENE HOWARD L , NAVIN ERIC R , LUCKE LORI E , MULLIN BENJAMIN T
IPC分类号： F04B43/02 , A61M5/142 , A61M5/168 , A61M5/172
CPC分类号： A61M5/14224 , A61M5/16809 , A61M5/16854 , A61M5/172 , A61M2205/128 , A61M2205/3331
摘要： A medical pump with an improved continuity low flow delivery system and method for use with a pumping chamber, for example in a cassette, is disclosed. The pump includes a pump drive for exerting a force on the pumping chamber and a sensor for sensing the force/pressure exerted by the pump drive on the pumping chamber. The pump drive position sensor senses the position of the pump drive. The medical pump also includes a processing unit and a memory having a programming code adapted to calculate the rate of change of the sensed force/pressure values and determine whether the rate of change of the sensed force/pressure values meets a rate of change threshold. Once the rate of change threshold is met, the programming code is adapted to calculate a remaining pump drive travel value for determining how much farther the pump drive should travel before the end of an effective pump cycle. The programming code is further adapted to trigger one or more signals to drive the pump drive for the remainder of the effective pump cycle using the remaining pump drive travel value.
摘要翻译：公开了一种具有改进的连续性低流量输送系统的医疗泵以及用于例如在盒中的泵送室的方法。泵包括用于在泵送室上施加力的泵驱动器和用于感测泵驱动器在泵送室上施加的力/压力的传感器。泵驱动位置传感器检测泵驱动器的位置。医疗泵还包括处理单元和具有适于计算检测到的力/压力值的变化率的编程代码的存储器，并且确定检测到的力/压力值的变化率是否满足变化率阈值。一旦满足了变化率阈值，编程代码就适用于计算剩余的泵驱动行程值，用于确定泵驱动器在有效泵循环结束之前要行进的距离。编程代码还适用于使用剩余的泵驱动行程值来触发一个或多个信号来驱动泵驱动器的剩余有效泵循环。

10. 发明申请

WO2007095080A2 MEMORY CIRCUIT SYSTEM AND METHOD 审中-公开
标题翻译：存储器电路系统和方法
公开(公告)号：WO2007095080A2
公开(公告)日：2007-08-23
申请号：PCT/US2007/003460
申请日：2007-02-08
申请人： RAJAN, Suresh, Natarajan , SMITH, Michael, John, Sebastian , SCHAKEL, Keith, R. , WANG, David, T. , WEBER, Frederick, Daniel
发明人： RAJAN, Suresh, Natarajan , SMITH, Michael, John, Sebastian , SCHAKEL, Keith, R. , WANG, David, T. , WEBER, Frederick, Daniel
CPC分类号： G06F13/4243
摘要： A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. In another embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits. In yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, a buffer circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, an interface circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system so to operate the memory stack as a single DRAM integrated circuit.
摘要翻译：提供了一种存储器电路系统和方法。在一个实施例中，接口电路能够与多个存储器电路和系统通信。在使用中，接口电路可操作以连接存储器电路和系统，以减少存储器电路的命令调度约束。在另一个实施例中，接口电路能够与多个存储器电路和系统通信。在使用中，接口电路可操作地转换与在系统和存储器电路之间传送的命令相关联的地址。在另一个实施例中，至少一个存储器堆叠包括多个DRAM集成电路。此外，耦合到主机系统的缓冲电路用于将存储器堆栈与主机系统进行接口，以便在DRAM集成电路和主机系统之间变换一个或多个物理参数。在又一实施例中，至少一个存储器堆叠包括多个DRAM集成电路。此外，耦合到主机系统的接口电路用于将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。

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