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1. 发明申请

WO2006033056A3 MICRO PROCESSOR DEVICE AND METHOD FOR SHUFFLE OPERATIONS 审中-公开
公开(公告)号：WO2006033056A3
公开(公告)日：2006-03-30
申请号：PCT/IB2005/053019
申请日：2005-09-14
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN BERKEL, Cornelis, H. , SRINIVASAN, Balakrishnan
发明人： VAN BERKEL, Cornelis, H. , SRINIVASAN, Balakrishnan
IPC分类号： G06F9/38 , G06F9/345
摘要： The present invention relates to a micro processor device comprising a vector processor architecture with a functional vector processor unit comprising first memory means for storing plural index vectors and processing means, the functional vector processor unit being arranged to receive a processing instruction and at least one input vector to be processed, said first memory means being arranged to provide the processing means with one of said plural index vectors in accordance with the processing instruction, and the processing means being arranged to generate in response to said instruction at least one output vector having the elements of the at least one input vector rearranged in accordance with the one index vector provided. The functional vector processor unit further comprises pre-processing means arranged to receive a parameter and to process the elements of the one index vector dependent on said parameter before generating said at least one output vector in accordance with the processed index vector. The invention further relates to a method for processing vectors with such a functional vector-processing unit.

2. 发明申请

WO2005026927A2 ELECTRONIC CIRCUIT WITH A CHAIN OF PROCESSING ELEMENTS 审中-公开
标题翻译：具有加工元件链的电子电路
公开(公告)号：WO2005026927A2
公开(公告)日：2005-03-24
申请号：PCT/IB2004051599
申请日：2004-08-30
申请人： KONINKL PHILIPS ELECTRONICS NV , PEETERS ADRIANUS M G , VAN BERKEL CORNELIS H , DE CLERCQ MARK N O
发明人： PEETERS ADRIANUS M G , VAN BERKEL CORNELIS H , DE CLERCQ MARK N O
IPC分类号： G06F1/32 , G06F9/38 , G06F15/78
CPC分类号： G06F15/8053 , G06F1/32
摘要： A chain of processing element (l0a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic circuit (14) of a next processing element (10a, 10, l 0b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (l0b) includes loading time points of loading all processing elements (l0a, 10) other than the final processing element (10).
摘要翻译：提供具有逻辑电路（14）和存储元件（12）的处理元件链（10a，10,10b）。除链中最终处理元件（10b）之外的所有存储元件（12）具有耦合到链中下一处理元件（10a，10,10b）的逻辑电路（14）的一个或多个输出。定时电路（16）控制存储元件（12）从处理元件（10a，10,10b）中的相应处理元件中的逻辑电路（14）加载数据的相应加载时间点。稍后将数据在处理元件（10a，10，10b）中连续地在链中先后加载。最终处理元件（10b）的连续加载时间点之间的时间间隔包括加载除最终处理元件（10）以外的所有处理元件（10a，10）的加载时间点。

3. 发明申请

WO2004049154A2 A LOOP CONTROL CIRCUIT FOR A DATA PROCESSOR 审中-公开
标题翻译：用于数据处理器的环路控制电路
公开(公告)号：WO2004049154A2
公开(公告)日：2004-06-10
申请号：PCT/IB2003/004962
申请日：2003-10-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUWISSEN, Patrick, P., E. , ENGIN, Nur , VAN BERKEL, Cornelis, H. , BEKOOIJ, Marco, J., G.
发明人： MEUWISSEN, Patrick, P., E. , ENGIN, Nur , VAN BERKEL, Cornelis, H. , BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/38
CPC分类号： G06F9/30181 , G06F9/325
摘要： A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at least an indication of an end of the loop and a loop count for indicating a number of times the loop should be executed. The loop control circuit (230) detects that one of the loops needs to be executed and in response to said detection, loads the loop information for the corresponding loop, and controls the program counter to execute the corresponding loop according to the loaded loop information. The loop information is initialized in response to a loop initialization instruction (240), where the initialization instruction is issued prior to and independent of a start of the loop initialized by the loop information.
摘要翻译：数据处理器（200）包括用于从由程序计数器（220）指示的指令存储器（210）执行指令的操作执行单元（225）。环路控制电路（230）将多个指令循环的相关联的环路信息存储在寄存器组（232）中。循环信息至少包括循环结束的指示和循环计数，用于指示应该执行循环的次数。环路控制电路（230）检测到需要执行一个环路，并响应于所述检测，加载相应环路的环路信息，并根据加载的环路信息控制程序计数器执行相应的环路。响应于循环初始化指令（240）初始化循环信息，其中初始化指令是在由循环信息初始化的循环的开始之前发出的。

4. 发明申请

WO2003100602A2 A SCALAR/VECTOR PROCESSOR 审中-公开
标题翻译：标量/矢量处理器
公开(公告)号：WO2003100602A2
公开(公告)日：2003-12-04
申请号：PCT/IB2003/002213
申请日：2003-05-22
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN BERKEL, Cornelis, H. , MEUWISSEN, Patrick, P., E. , ENGIN, Nur
发明人： VAN BERKEL, Cornelis, H. , MEUWISSEN, Patrick, P., E. , ENGIN, Nur
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3834 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3893 , G06F15/8061
摘要： A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.
摘要翻译：标量/矢量处理器包括多个功能单元（252,260,262,264,266,268,270）。至少一个功能单元包括用于在至少一个矢量上操作的矢量部分（210）和用于在至少一个标量上操作的标量部分（220）。功能单元的矢量部分和标量部分由标量部分协作，被布置成提供和/或消耗由功能单元的向量部分所要求的和/或由其提供的至少一个标量。

5. 发明申请

WO2008018004A3 ELECTRONIC DEVICE AND METHOD FOR SYNCHRONIZING A COMMUNICATION 审中-公开
标题翻译：用于同步通信的电子设备和方法
公开(公告)号：WO2008018004A3
公开(公告)日：2008-05-22
申请号：PCT/IB2007053086
申请日：2007-08-06
申请人： KONINKL PHILIPS ELECTRONICS NV , TIMMERMANS DANIEL , VAN BERKEL CORNELIS H , BINK ADRIANUS J
发明人： TIMMERMANS DANIEL , VAN BERKEL CORNELIS H , BINK ADRIANUS J
IPC分类号： G06F15/78 , H04L12/00
CPC分类号： H04L49/40 , G06F15/7825 , H04L45/00 , H04L45/60 , H04L49/109 , H04L49/1546 , Y02D10/12 , Y02D10/13
摘要： An electronic device is provided which comprises a plurality of processing units (IPl - IP6) and a flit-synchronous network-based interconnect (N) for coupling the processing units (IPl - IP6). The network-based interconnect (N) comprises at least one first and at least one second link. The at least one second link comprises N pipeline stages. The communication via the at least one second link and the N pipeline stages constitutes a word- asynchronous communication.
摘要翻译：提供了一种电子设备，其包括用于耦合处理单元（IP1-IP6）的多个处理单元（IP1-IP6）和基于快速同步的基于网络的互连（N）。基于网络的互连（N）包括至少一个第一链路和至少一个第二链路。该至少一个第二链路包括N个流水线级。经由至少一个第二链路和N个流水线级的通信构成字异步通信。

6. 发明申请

WO2008018004A2 ELECTRONIC DEVICE AND METHOD FOR SYNCHRONIZING A COMMUNICATION 审中-公开
标题翻译：电子设备和用于同步通信的方法
公开(公告)号：WO2008018004A2
公开(公告)日：2008-02-14
申请号：PCT/IB2007/053086
申请日：2007-08-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TIMMERMANS, Daniel , VAN BERKEL, Cornelis, H. , BINK, Adrianus, J.
发明人： TIMMERMANS, Daniel , VAN BERKEL, Cornelis, H. , BINK, Adrianus, J.
IPC分类号： G06F15/78 , H04L12/00
CPC分类号： H04L49/40 , G06F15/7825 , H04L45/00 , H04L45/60 , H04L49/109 , H04L49/1546 , Y02D10/12 , Y02D10/13
摘要： An electronic device is provided which comprises a plurality of processing units (IPl - IP6) and a flit-synchronous network-based interconnect (N) for coupling the processing units (IPl - IP6). The network-based interconnect (N) comprises at least one first and at least one second link. The at least one second link comprises N pipeline stages. The communication via the at least one second link and the N pipeline stages constitutes a word- asynchronous communication.
摘要翻译：提供了一种电子设备，其包括多个处理单元（IP1-IP6）和用于耦合处理单元（IP1-IP6）的基于飞行同步网络的互连（N）。基于网络的互连（N）包括至少一个第一和至少一个第二链路。所述至少一个第二链路包括N个流水线级。经由至少一个第二链路和N个流水线级的通信构成字异步通信。

7. 发明申请

WO2007063450A2 TV-PC ARCHITECTURE 审中-公开
标题翻译：电视机架构
公开(公告)号：WO2007063450A2
公开(公告)日：2007-06-07
申请号：PCT/IB2006054361
申请日：2006-11-21
申请人： KONINKL PHILIPS ELECTRONICS NV , DE HAAN GERARD , VAN BERKEL CORNELIS H
发明人： DE HAAN GERARD , VAN BERKEL CORNELIS H
CPC分类号： G06F3/1438 , G06F3/14 , H04N21/414
摘要： An apparatus includes at least a first hardware part (AP1) and a second hardware part (AP2). Each of the first and second part include a respective processing element (CPU-1, CPU-2) and a respective signal connection to a respective memory element (MEM-1, MEM-2) for providing program code to the processing element of the respective part. The apparatus further includes a third hardware part (AP3) including at least one peripheral element acting as a source and/or destination of data. A fourth hardware part of the apparatus includes an I/O network (AP-4) for enabling communication between elements of the first and third part under control of first configuration data and for enabling communication between elements of the second and third part under control of distinct second configuration data.
摘要翻译：一种装置至少包括第一硬件部分（AP1）和第二硬件部分（AP2）。第一和第二部分中的每一个包括相应的处理元件（CPU-1，CPU-2）和与各个存储元件（MEM-1，MEM-2）的信号连接，用于向程序代码提供程序代码各自的部分。该装置还包括第三硬件部分（AP3），其包括用作数据的源和/或目的地的至少一个外围元素。该装置的第四硬件部分包括一个I / O网络（AP-4），用于在第一和第三部分的元件之间进行通信，在第一配置数据的控制下，以及在第二和第三部分的元件之间进行通信，明确的第二个配置数据。

8. 发明申请

WO2004049154A3 A LOOP CONTROL CIRCUIT FOR A DATA PROCESSOR 审中-公开
标题翻译：用于数据处理器的环路控制电路
公开(公告)号：WO2004049154A3
公开(公告)日：2005-01-20
申请号：PCT/IB0304962
申请日：2003-10-31
申请人： KONINKL PHILIPS ELECTRONICS NV , MEUWISSEN PATRICK P E , ENGIN NUR , VAN BERKEL CORNELIS H , BEKOOIJ MARCO J G
发明人： MEUWISSEN PATRICK P E , ENGIN NUR , VAN BERKEL CORNELIS H , BEKOOIJ MARCO J G
IPC分类号： G06F9/318 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/325
摘要： A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at least an indication of an end of the loop and a loop count for indicating a number of times the loop should be executed. The loop control circuit (230) detects that one of the loops needs to be executed and in response to said detection, loads the loop information for the corresponding loop, and controls the program counter to execute the corresponding loop according to the loaded loop information. The loop information is initialized in response to a loop initialization instruction (240), where the initialization instruction is issued prior to and independent of a start of the loop initialized by the loop information.
摘要翻译：数据处理器（200）包括用于从由程序计数器（220）指示的指令存储器（210）执行指令的操作执行单元（225）。环路控制电路（230）将多个指令循环的相关联的环路信息存储在寄存器组（232）中。循环信息至少包括循环结束的指示和循环计数，用于指示应该执行循环的次数。环路控制电路（230）检测到需要执行一个环路，并响应于所述检测，加载相应环路的环路信息，并根据加载的环路信息控制程序计数器执行相应的环路。响应于循环初始化指令（240）初始化循环信息，其中初始化指令是在由循环信息初始化的循环的开始之前发出的。

9. 发明申请

WO2003100599A2 ACCESS TO A WIDE MEMORY 审中-公开
标题翻译：访问一个宽的内存
公开(公告)号：WO2003100599A2
公开(公告)日：2003-12-04
申请号：PCT/IB2003/001891
申请日：2003-05-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN BERKEL, Cornelis, H. , MEUWISSEN, Patrick, P., E.
发明人： VAN BERKEL, Cornelis, H. , MEUWISSEN, Patrick, P., E.
IPC分类号： G06F9/30
CPC分类号： G06F9/3893 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3834 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F15/8061
摘要： A processing system includes a processor and a physical memory (500) with a single-size memory port (505) for accessing data in the memory. The processor is arranged to operate on data of at least a first data size and a smaller second data size. The first data size is equal to or smaller than the size of memory port. The processing system including at least one data register (514) of the first data size connected to the memory port (505), and at least one data port (525) of the second data size connected to the data register (525) and the processor for enabling access to data elements of the second size.
摘要翻译：处理系统包括具有用于访问存储器中的数据的单个大小的存储器端口（505）的处理器和物理存储器（500）。处理器被布置成对至少第一数据大小和较小的第二数据大小的数据进行操作。第一个数据大小等于或小于存储器端口的大小。所述处理系统包括连接到存储器端口（505）的第一数据大小的至少一个数据寄存器（514）和连接到数据寄存器（525）的第二数据大小的至少一个数据端口（525）和处理器，用于允许访问第二大小的数据元素。

10. 发明申请

WO02101926A3 INTEGRATED CIRCUIT AND METHOD FOR TESTING THE INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路和测试集成电路的方法
公开(公告)号：WO02101926A3
公开(公告)日：2003-02-20
申请号：PCT/IB0202206
申请日：2002-06-10
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN BERKEL CORNELIS H , PEETERS ADRIANUS M G
发明人： VAN BERKEL CORNELIS H , PEETERS ADRIANUS M G
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/822 , H01L27/04 , H03K3/037 , H03K3/356 , H03K19/00 , H03K19/20
CPC分类号： G01R31/318594 , G01R31/318541 , G01R31/318552 , H03K3/0375
摘要： An integrated circuit according to the invention comprises a plurality of units (C1, C2, C3, C4;1), having first inputs (2a, 2b, 2c) for receiving control signals (n,s,t) for setting an operational mode of the unit (1). The units (1) have a functional mode, a scan in mode, a scan out mode. In the functional mode (n=1,s=0,t=1) a logical operation is performed at signals (a,b) received at one or more second inputs (4a, 4b). The result of the logical operation is provided via an internal node (6) to an output (10). In the scan in mode (n=0,s=1,t=0) a value at a scan input is stored at the internal node (6). In the scan out mode (n=0,s=0,t=1) the value at the internal node (6) is provided to the output (10). The integrated circuit according to the invention further has an evaluate mode (n=1,s=0,t=0) in which the result of the logical operation at the input signals (a,b) is stored at the internal node (6), and in which the output (10) of the units is disabled.
摘要翻译：根据本发明的集成电路包括多个单元（C1，C2，C3，C4; 1），具有用于接收用于设置操作模式的控制信号（n，s，t）的第一输入端（2a，2b，2c）的单元（1）。单元（1）具有功能模式，扫描模式，扫描输出模式。在功能模式（n = 1，s = 0，t = 1）中，在一个或多个第二输入（4a，4b）处接收的信号（a，b）执行逻辑运算。逻辑运算的结果经由内部节点（6）提供给输出（10）。在扫描模式（n = 0，s = 1，t = 0）中，扫描输入处的值存储在内部节点（6）处。在扫描输出模式（n = 0，s = 0，t = 1）中，内部节点（6）的值被提供给输出（10）。根据本发明的集成电路还具有在输入信号（a，b）处的逻辑运算的结果存储在内部节点（6）处的评估模式（n = 1，s = 0，t = 0）），并且其中单元的输出（10）被禁用。

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