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    • 2. 发明申请
    • DEVICE AND METHOD FOR COMPOSING CODES
    • 用于组合编码的装置和方法
    • WO2005008474A1
    • 2005-01-27
    • PCT/IB2004/051201
    • 2004-07-13
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.VAN BERKEL, Cornelis, H.MEUWISSEN, Patrick, P., E.NAS, Ricky, J., M.
    • VAN BERKEL, Cornelis, H.MEUWISSEN, Patrick, P., E.NAS, Ricky, J., M.
    • G06F7/58
    • H04J13/105
    • Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for related functions such as cyclic redundancy check (CRC). A configurable vector processor would then be equipped with a plurality of generators which generate basic codes in vector format. However, a disadvantage of such a configurable vector processor is that it cannot provide a composite code which is dependent on such basic codes. This is necessary if the configurable vector processors should be flexible enough to support a variety of CDMA-like standards. The device according to the invention is provided with at least two weighted sum units, which are able to make a selection out of a plurality of incoming basic-code vectors by means of a weighted sum operation, under the control of a configuration word. The elements of this configuration word represent the weighting factors which are used to select or deselect a basic-code vector. The selected basic-code vectors are added together and the result of the weighted sum operation is then output as an intermediate-code vector. Subsequently, the intermediate-code vectors are added together by an add unit and output as a composite-code vector. The ability to make selections out of a plurali ty of incoming basic-code vectors and to add intermediate-code vectors into a composite-code vector, together with the ability to configure the operations of the functional units of the device by means of configuration words, increases the flexibility of the device significantly. This flexibility is needed to support a variety of transmission standards.
    • 可配置向量处理器可以配备代码生成器,以便它们能够处理不同的标准和代码。 此外,它们可以被布置成为诸如循环冗余校验(CRC)之类的相关功能提供支持。 然后,可配置的向量处理器将配备有以矢量格式生成基本代码的多个生成器。 然而,这种可配置向量处理器的缺点在于它不能提供依赖于这种基本代码的复合代码。 如果可配置矢量处理器应足够灵活以支持各种类似CDMA的标准,则这是必要的。 根据本发明的装置具有至少两个加权和单元,它们能够在配置字的控制下通过加权和运算从多个输入的基本码矢量中进行选择。 该配置字的元素表示用于选择或取消选择基本码矢量的加权因子。 将所选择的基本码向量相加,然后将加权和运算的结果作为中间码矢量输出。 随后,通过加法单元将中间码矢量相加在一起,作为复合码矢量输出。 能够从多个输入的基本代码向量中进行选择,并将中间代码向量添加到复合代码向量中,以及通过配置字来配置设备的功能单元的操作的能力 ,显着增加了设备的灵活性。 需要这种灵活性来支持各种传输标准。
    • 4. 发明申请
    • ENHANCING PERFORMANCE OF A MEMORY UNIT OF A DATA PROCESSING DEVICE BY SEPARATING READING AND FETCHING FUNCTIONALITIES
    • 通过分离读取和切断功能来提高数据处理设备的存储单元的性能
    • WO2006087665A3
    • 2007-01-18
    • PCT/IB2006050461
    • 2006-02-13
    • KONINKL PHILIPS ELECTRONICS NVPETERS HARM J A MSETHURAMAN RAMANATHANVELDMAN GERARDMEUWISSEN PATRICK P E
    • PETERS HARM J A MSETHURAMAN RAMANATHANVELDMAN GERARDMEUWISSEN PATRICK P E
    • G06F12/08
    • H04N19/433G06F12/0862G06F12/0875G06F12/0897G06T7/20G06T2200/28G09G5/395G09G2320/0261G09G2360/121H04N19/436
    • The present invention relates to a data processing device (10) comprising a processing unit (12) and a memory unit (14), and to a method for controlling operation of a memory unit (14) of a data processing device. The memory unit (14) comprises a main memory (16), a low- level cache memory (20.2), which is directly connected to the processing unit (12) and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (12), a high-level cache memory (18), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (20.1), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan order followed by the processing unit. Reading and fetching functionalities are decoupled in the memory unit (14). The fetching functionality is concentrated on the higher cache level, while the reading functionality is concentrated on the lower cache level. This way concurrent reading and fetching can be achieved, thus enhancing the performance of a data processing device.
    • 本发明涉及包括处理单元(12)和存储单元(14)的数据处理设备(10),以及用于控制数据处理设备的存储单元(14)的操作的方法。 存储器单元(14)包括主存储器(16),低级高速缓存存储器(20.2),其直接连接到处理单元(12)并且适于保持当前活动的滑动搜索区域的所有像素用于读取 处理单元(12)的访问,连接在低级缓存存储器和帧存储器之间的高级缓存存储器(18)和第一预取缓冲器(20.1) 高级缓存存储器和低级高速缓存存储器,并且其适于保持像素块的一个搜索区域列或一个搜索区域行,这取决于处理单元后面的扫描方向和扫描顺序。 读取和取出功能在存储器单元(14)中解耦。 获取功能集中在较高的缓存级别,而读取功能集中在较低的缓存级别。 这样可以实现并行读取和取出,从而提高数据处理设备的性能。
    • 9. 发明申请
    • SEGMENTATION OF AN IMAGE
    • 图像分割
    • WO2006082541A2
    • 2006-08-10
    • PCT/IB2006050264
    • 2006-01-25
    • KONINKL PHILIPS ELECTRONICS NVERNST FABIAN EMEUWISSEN PATRICK P E
    • ERNST FABIAN EMEUWISSEN PATRICK P E
    • G06T7/00H04N13/00
    • H04N13/026G06T7/215G06T2207/10016
    • The invention concerns a method, device and computer program product for segmenting an image in a signal as well as a device for providing a multi-dimensional image. In the device (32) for segmenting an image there is provided a segmenting unit (48) arranged to apply a segmentation scheme to images, and a control unit (44) arranged to divide a present image (I2) in the signal into a number of regions (10), select a limited number of regions, order said segmenting unit to apply said segmentation scheme on said selected regions that provides at least one fresh segment, and provide at least one segment (S) created for a previous image (I1) in the signal to the other regions of the present image. In this way the required computational power is reduced while at the same time providing a balance between the accuracy and temporal consistency requirements for the segmentations.
    • 本发明涉及用于分割信号中的图像的方法,装置和计算机程序产品以及用于提供多维图像的装置。 在用于分割图像的装置(32)中,提供了一种分割单元(48),其被布置为对图像应用分割方案;以及控制单元(44),其被布置为将该信号中的当前图像(I2)分成数字 (10)选择有限数量的区域,命令所述分割单元将所述分割方案应用于提供至少一个新分段的所述选择的区域上,并提供为先前图像(I1)创建的至少一个分段(S) )到当前图像的其他区域的信号。 以这种方式,减少所需的计算能力,同时在分段的精度和时间一致性要求之间提供平衡。