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1. 发明申请

WO2018035515A1 TEST STACK HAVING WAFER TRANSLATOR AND STIFFENING INTERFACE, AND ASSOCIATED SYSTEMS AND METHODS 审中-公开
标题翻译：具有晶片翻译器和加强界面的测试堆栈以及相关的系统和方法
公开(公告)号：WO2018035515A1
公开(公告)日：2018-02-22
申请号：PCT/US2017/047756
申请日：2017-08-21
申请人： TRANSLARITY, INC.
发明人： LANE, Christopher, T.
IPC分类号： G01R31/26 , B23K31/02 , G01R1/04 , G01R1/073 , G01R3/00 , G01R31/28
CPC分类号： G01R31/2889 , G01R1/06722 , G01R1/07378
摘要： Systems and methods for testing semiconductor wafers are disclosed herein. In one embodiment, an apparatus for testing dies of a semiconductor wafer includes: a wafer translator having a wafer-side configured to face the wafer, and an inquiry-side facing away from the wafer-side. The wafer-side carries wafer-side contact structures, and the inquiry-side carries inquiry-side contact structures. The apparatus also includes a stiffening interface (SIF) board having a first side facing the inquiry-side of the wafer translator, and a second side facing away from the first side. The apparatus also includes a tester translator interface (TTI) board having a first face facing the second side of the SIF, and a second face facing away from the first face.
摘要翻译：这里公开了用于测试半导体晶片的系统和方法。在一个实施例中，一种用于测试半导体晶片的管芯的设备包括：晶片转换器，具有配置成面对晶片的晶片侧和面向晶片侧的查询侧。晶片侧承载晶片侧接触结构，并且查询侧承载查询侧接触结构。该装置还包括加强界面（SIF）板，其具有面向晶片转换器的查询侧的第一侧和面向远离第一侧的第二侧。该设备还包括具有面向SIF的第二侧的第一面和背向第一面的第二面的测试器翻译器接口（TTI）板。

2. 发明申请

WO2018035054A1 SPACE TRANSFORMERS FOR PROBE CARDS, AND ASSOCIATED SYSTEMS AND METHODS 审中-公开
标题翻译：用于探针卡的空间变换器以及相关的系统和方法
公开(公告)号：WO2018035054A1
公开(公告)日：2018-02-22
申请号：PCT/US2017/046791
申请日：2017-08-14
申请人： TRANSLARITY, INC.
发明人： SPORCK, Alistair Nicholas
IPC分类号： G01R1/067 , G01R1/073 , G01R3/00 , G01R31/02 , G01R31/28
CPC分类号： G01R31/2889 , G01R1/07378
摘要： Systems and methods for testing semiconductor wafers are disclosed herein. In one embodiment, an apparatus for testing dies of a semiconductor wafer includes a composite space transformer for contacting the dies. The composite space transformer has a first space transformer having a first side configured to face the wafer, and a second side facing away from the wafer. The first space transformer has a substrate made of ceramic. The composite space transformer also has a second space transformer having a first side configured to face the wafer, and a second side facing the first side of the first space transformer. The second space transformer has a substrate made of glass. The composite space transformer has a space transformer interconnect to electrically connect the first space transformer and the second space transformer.
摘要翻译：这里公开了用于测试半导体晶片的系统和方法。在一个实施例中，用于测试半导体晶片的管芯的装置包括用于接触管芯的复合空间变换器。该复合空间变换器具有第一空间变换器，该第一空间变换器具有被配置为面对晶片的第一侧和面向远离晶片的第二侧。第一个空间变换器具有由陶瓷制成的基板。该组合式空间变换器还具有第二空间变换器，该第二空间变换器具有被配置成面向晶片的第一侧和面向第一空间变换器的第一侧的第二侧。第二空间变换器具有由玻璃制成的基板。复合空间变压器具有空间互感器互连以电连接第一空间变压器和第二空间变压器。

3. 发明申请

WO2021258087A2 REDISTRIBUTION PLATE 审中-公开
公开(公告)号：WO2021258087A2
公开(公告)日：2021-12-23
申请号：PCT/US2021/049159
申请日：2021-09-03
申请人： TRANSLARITY, INC.
发明人： SCHMIDT, Dominik , CHITTURI, Prasanna , HSU, Jed
IPC分类号： G01R1/04 , G01R31/28 , G01R31/319 , H05K1/02
摘要： A single-layer redistribution plate functioning as a space translator between a device under testing ("DUT") and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

4. 发明申请

WO2018089659A1 PROBE CARD ASSEMBLY HAVING DIE-LEVEL AND PIN-LEVEL COMPLIANCE, AND ASSOCIATED SYSTEMS AND METHODS 审中-公开
标题翻译：探针卡组件具有死穴级别和针脚级别的遵从性，以及相关的系统和方法
公开(公告)号：WO2018089659A1
公开(公告)日：2018-05-17
申请号：PCT/US2017/060897
申请日：2017-11-09
申请人： TRANSLARITY, INC.
发明人： SUNDBY, Ray, Lyle , MARTINEZ, Claudio , LANE, Christopher, T. , CHITTURI, Prasanna, Rao , SPORCK, Alistair, Nicholas , PRESTON, Douglas, A.
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28
CPC分类号： G01R1/07378 , G01R1/0491 , G01R1/0735
摘要： Systems and methods for testing semiconductor wafers are disclosed herein. In one embodiment, an apparatus for testing dies of a semiconductor wafer includes: a tester-side printed circuit board (PCB); a wafer-side support plate having a first surface facing the tester-side PCB and a second surface facing away from the first face; and a plurality of individual probe cards (DUT-lets) supported by the wafer-side support plate. Each individual DUT-let has a DUT-let contactor that carries a plurality of contact structures for contacting at least one die of the semiconductor wafer. The individual DUT-let contactors are individually compliant with respect to the semiconductor wafer, and wherein the individual DUT-let contactors are separated.
摘要翻译：这里公开了用于测试半导体晶片的系统和方法。在一个实施例中，用于测试半导体晶片的管芯的设备包括：测试器侧印刷电路板（PCB）晶片侧支撑板，其具有面向所述测试器侧PCB的第一表面和背向所述第一面的第二表面; 和由晶片侧支撑板支撑的多个单独探针卡（DUT-let）。每个单独的DUT-let具有一个DUT-let接触器，其承载用于接触半导体晶片的至少一个管芯的多个接触结构。单独的DUT-let接触器独立于半导体晶片，并且其中单独的DUT-let接触器是分开的。

5. 发明申请

WO2018009940A1 STACKED STUD BUMP CONTACTS FOR WAFER TEST CONTACTORS, AND ASSOCIATED METHODS 审中-公开
标题翻译：用于晶片测试接触器的堆叠式焊接漏磁触点以及相关方法
公开(公告)号：WO2018009940A1
公开(公告)日：2018-01-11
申请号：PCT/US2017/041401
申请日：2017-07-10
申请人： TRANSLARITY, INC.
发明人： SPORCK, Alistair, Nicholas , GRUBE, Gary , JOHNSON, Morgan, T.
IPC分类号： H01L23/00 , H01L23/498 , H01L25/11 , G01R1/073
摘要： Systems and methods for testing semiconductor wafers are disclosed herein. In one embodiment, an apparatus for testing dies on a semiconductor wafer includes a test contactor for contacting the dies. The test contactor has a substrate having a wafer-side facing the wafer, and an inquiry-side facing away from the wafer-side. The test contactor also has a wafer-side contact pad carried by the wafer-side of the substrate, and a stud bump pin attached to the wafer-side contact pad. The stud bump pin terminates in a stud bump tip for probing a contact pad of a die.
摘要翻译：这里公开了用于测试半导体晶片的系统和方法。在一个实施例中，用于测试半导体晶片上的管芯的设备包括用于接触管芯的测试接触器。测试接触器具有衬底，该衬底具有面向晶片的晶片侧和面向晶片侧的查询侧。测试接触器还具有由衬底的晶片侧承载的晶片侧接触垫和附着于晶片侧接触垫的柱凸块引脚。柱形凸块引脚终止于柱形凸块顶端，用于探测裸片的接触板。

6. 发明申请

WO2016201327A1 SYSTEMS AND METHODS FOR GENERATING AND PRESERVING VACUUM BETWEEN SEMICONDUCTOR WAFER AND WAFER TRANSLATOR 审中-公开
标题翻译：用于生成和保存半导体波形和波长转换器之间的真空的系统和方法
公开(公告)号：WO2016201327A1
公开(公告)日：2016-12-15
申请号：PCT/US2016/037023
申请日：2016-06-10
申请人： TRANSLARITY, INC.
发明人： KALNIN, Nikolai , LANE, Christopher, T. , EKSTROM, David , JOHNSON, Morgan, T. , PRESTON, Douglas, A.
IPC分类号： G01R31/20 , G01R31/26
CPC分类号： G01R31/2891 , F04B37/14 , G01R1/0466 , G01R31/2893 , H01L21/67144 , H01L21/67242 , H01L21/677 , H01L21/6838 , H01L22/14
摘要： Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for testing semiconductor dies on a wafer includes a wafer translator having a wafer-side facing toward the wafer, and an inquiry-side facing away from the wafer-side. The wafer has an active side facing the translator. The apparatus includes a peripheral seal configured to seal a space between the wafer translator and the wafer, and a valve in a fluidic communication with the space between the wafer translator and the wafer.
摘要翻译：本文公开了使用晶片转换器测试半导体晶片的系统和方法。在一个实施例中，用于在晶片上测试半导体管芯的装置包括具有晶片侧面向晶片的晶片转换器和面向晶片侧的查询侧。晶片具有面向平移器的有源侧。该装置包括构造成密封晶片转换器和晶片之间的空间的外围密封件，以及与晶片转换器和晶片之间的空间流体连通的阀。

7. 发明申请

WO2016201289A1 SHAPING OF CONTACT STRUCTURES FOR SEMICONDUCTOR TEST, AND ASSOCIATED SYSTEMS AND METHODS 审中-公开
标题翻译：形成用于半导体测试的接触结构，以及相关系统和方法
公开(公告)号：WO2016201289A1
公开(公告)日：2016-12-15
申请号：PCT/US2016/036973
申请日：2016-06-10
申请人： TRANSLARITY, INC.
发明人： RUFFLER, Jens , PRESTON, Douglas A. , LANE, Christopher T. , AITKEN, Thomas
IPC分类号： B23Q17/20 , G01N13/00 , G01N21/95 , G01R31/02 , G01R31/26
CPC分类号： G01R1/07378 , G01R31/26 , G01R31/2889 , H01L21/6838 , H01L24/741 , H01L2224/749
摘要： Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for adjusting a wafer translator for testing semiconductor dies includes the semiconductor wafer translator having a wafer translator substrate with a wafer-side configured to face the dies. A plurality of wafer-side contact structures is carried by the wafer-side of the wafer translator. The apparatus also includes a shaping wafer having a shaping wafer substrate, and a plurality of cavities in the shaping wafer substrate. The wafer-side contact structures are shaped by contacting surfaces of the cavities of the shaping wafer substrate.
摘要翻译：本文公开了使用晶片转换器测试半导体晶片的系统和方法。在一个实施例中，用于调整用于测试半导体管芯的晶片转换器的装置包括半导体晶片转换器，其具有晶片转换器基板，晶片侧被配置为面对模具。多个晶片侧接触结构由晶片转换器的晶片侧承载。该装置还包括具有成形晶片衬底的成形晶片和成形晶片衬底中的多个空腔。晶片侧接触结构通过接触成形晶片基板的空腔的表面而成形。

8. 发明申请

WO2016200633A1 INTERDIGITIZED POLYSYMMETRIC FANOUTS, AND ASSOCIATED SYSTEMS AND METHODS 审中-公开
标题翻译：互联多极化飞行器及相关系统和方法
公开(公告)号：WO2016200633A1
公开(公告)日：2016-12-15
申请号：PCT/US2016/034787
申请日：2016-05-27
申请人： TRANSLARITY, INC.
发明人： JOHNSON, Morgan, T.
IPC分类号： G01R31/26 , G01R31/28 , H01L23/12 , H01L21/68
CPC分类号： G01R1/07378 , G01R31/2889 , H01L21/6838 , H01L22/32 , H01L24/06
摘要： Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for testing semiconductor dies includes a wafer translator having a wafer-side facing the dies and an inquiry-side facing away from the wafer-side. The inquiry-side of the wafer translator carries a first and a second plurality of inquiry-side contact structures. The first plurality of the inquiry-side contact structures is interleaved with the second plurality of the inquiry-side contact structures.
摘要翻译：本文公开了使用晶片转换器测试半导体晶片的系统和方法。在一个实施例中，用于测试半导体管芯的装置包括具有面向模具的晶片侧和背离晶片侧的询问侧的晶片转换器。晶片转换器的询问侧携带第一和第二多个查询侧接触结构。第一多个查询侧接触结构与第二多个查询侧接触结构交错。

9. 发明申请

WO2016200630A1 LOST MOTION GASKET FOR SEMICONDUCTOR TEST, AND ASSOCIATED SYSTEMS AND METHODS 审中-公开
标题翻译：用于半导体测试的失效运动垫圈及相关系统和方法
公开(公告)号：WO2016200630A1
公开(公告)日：2016-12-15
申请号：PCT/US2016/034669
申请日：2016-05-27
申请人： TRANSLARITY, INC.
发明人： PRESTON, Douglas A. , LANE, Christopher T. , GARDINER, Mark , JOHNSON, Morgan T. , BUCK, Douglas , KALNIN, Nikolai
IPC分类号： G01R31/26
CPC分类号： G01R31/2891 , G01R1/0466 , G01R1/07378 , G01R31/2889
摘要： Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for testing semiconductor dies includes a semiconductor wafer translator having a wafer-side positioned to face toward a device under test, and an inquiry-side facing away from the wafer-side. The apparatus also includes a flexible arm peripherally connected to the wafer translator, and an evacuation opening within the flexible arm or within the wafer translator. The evacuation opening is open to a flow of a gas in a first position of the flexible arm, and closed to a flow of the gas in a second position of the flexible arm.
摘要翻译：本文公开了使用晶片转换器测试半导体晶片的系统和方法。在一个实施例中，用于测试半导体管芯的设备包括半导体晶片转换器，其具有面向被测器件的晶片侧，以及面向晶片侧的查询侧。该装置还包括外围连接到晶片转换器的柔性臂以及柔性臂内或晶片转换器内的抽空开口。排气开口对于柔性臂的第一位置中的气体流开放，并且在柔性臂的第二位置中关闭到气体流。

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