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1. 发明申请

WO2014006451A1 DATA PATH CONFIGURATION COMPONENT, SIGNAL PROCESSING DEVICE AND METHOD THEREFOR 审中-公开
标题翻译：数据路径配置组件，信号处理设备及其方法
公开(公告)号：WO2014006451A1
公开(公告)日：2014-01-09
申请号：PCT/IB2012/053386
申请日：2012-07-03
申请人： FREESCALE SEMICONDUCTOR, INC. , ROBERTSON, Alistair , THANNER, Manfred
发明人： ROBERTSON, Alistair , THANNER, Manfred
IPC分类号： G06F1/00
CPC分类号： G06F13/4221 , G06F1/3203 , G06F1/3243 , G06F9/44505 , G06F13/4022 , Y02D10/152
摘要： A data path configuration component for configuring at least one data path setting within a signal processing device is described. The data path configuration component is arranged to receive an indication of an operating mode of the signal processing device, and dynamically configure the at least one data path setting within the signal processing device based at least partially on the received indication of an operating mode of the signal processing device.
摘要翻译：描述用于配置信号处理设备内的至少一个数据路径设置的数据路径配置组件。数据路径配置组件被布置成接收信号处理设备的操作模式的指示，并且至少部分地基于接收到的信号处理设备的操作模式的指示来动态地配置信号处理设备内的至少一个数据路径设置信号处理装置。

2. 发明申请

WO2014177905A1 DEVICE HAVING A SECURITY MODULE 审中-公开
标题翻译：具有安全模块的设备
公开(公告)号：WO2014177905A1
公开(公告)日：2014-11-06
申请号：PCT/IB2013/053400
申请日：2013-04-30
申请人： FREESCALE SEMICONDUCTOR, INC. , FRANK, Juergen , STAUDENMAIER, Michael , THANNER, Manfred
发明人： FRANK, Juergen , STAUDENMAIER, Michael , THANNER, Manfred
IPC分类号： G06F21/70
CPC分类号： G06F21/79 , G06F12/0223 , G06F12/1408 , G06F21/85 , G06F2212/1052
摘要： A device (100) is for securely accessing data in a memory via an addressing unit (120) which provides a memory interface (124) for interfacing to a memory (140), a core interface (121 ) for interfacing to a core processor (130) and a first and second security interface (123,122). The device comprises a security processor HSM (102) for performing at least one security operation on the data and a remapping unit MMAP (101 ). The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. Advantageously the device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.
摘要翻译：设备（100）用于经由寻址单元（120）安全访问存储器中的数据，所述寻址单元提供用于与存储器（140）进行接口的存储器接口（124），用于与核心处理器 130）和第一和第二安全接口（123,122）。该设备包括用于对数据执行至少一次安全操作的安全处理器HSM（102）和重映射单元MMAP（101）。重新映射单元使得安全处理器能够由核心处理器经由第一安全接口访问，并且经由第二安全接口根据重映射结构访问存储设备，以便基于存储器数据进行可访问的处理数据。有利的是，该设备提供对加密存储器数据的清晰视图，而不需要用于存储清除数据的系统存储器。

3. 发明申请

WO2013182872A1 BUILT-IN SELF TEST SYSTEM, SYSTEM ON A CHIP AND METHOD FOR CONTROLLING BUILT-IN SELF TESTS 审中-公开
标题翻译：内置自检系统，芯片系统和控制内置自检测试方法
公开(公告)号：WO2013182872A1
公开(公告)日：2013-12-12
申请号：PCT/IB2012/052879
申请日：2012-06-07
申请人： FREESCALE SEMICONDUCTOR, INC. , THANNER, Manfred , CULSHAW, Carl , FRANK, Juergen , STAUDENMAIER, Michael
发明人： THANNER, Manfred , CULSHAW, Carl , FRANK, Juergen , STAUDENMAIER, Michael
IPC分类号： G01R31/28
CPC分类号： G01R31/2856 , G01R31/31701 , G01R31/31721
摘要： A built-in self test system (10) comprises an integrated circuit device (12) comprising a plurality of functional units (14, 16, 18, 20) coupled to built-in self test circuitry (22, 24, 26, 28); a low power control unit (30) operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built- in self test control unit (32) coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.
摘要翻译：内置自检系统（10）包括集成电路装置（12），其包括耦合到内置自测电路（22,24,26,28）的多个功能单元（14,16,18,20） ; 低功率控制单元（30），其可操作以将所述集成电路装置切换到低功率模式并在进入所述低功率模式期间或之前产生BIST唤醒信号; 以及耦合到内置自测试电路和低功率控制单元的内置自检控制单元（32），并且被布置成在接收到BIST唤醒信号时启动内置自检。

4. 发明申请

WO2004051925A3 SYSTEM NODE AND METHOD FOR PROVIDING MEDIA ARBITRATION IN A TIME-SLOTTED SYSTEM 审中-公开
标题翻译：用于在时间系统中提供媒体仲裁的系统节点和方法
公开(公告)号：WO2004051925A3
公开(公告)日：2004-08-05
申请号：PCT/EP0350868
申请日：2003-11-21
申请人： MOTOROLA INC , TEMPLE CHRISTOPHER , BOGENBERGER FLORIAN , RAUSCH MATHIAS , THANNER MANFRED , WUERZ THOMAS , LINK LEONARD , POKORNY GREGOR
发明人： TEMPLE CHRISTOPHER , BOGENBERGER FLORIAN , RAUSCH MATHIAS , THANNER MANFRED , WUERZ THOMAS , LINK LEONARD , POKORNY GREGOR
IPC分类号： H04L12/407 , H04L12/64 , B60R16/02
CPC分类号： H04L12/417 , H04L12/413 , H04L12/6418 , H04L2012/40241 , H04L2012/40273 , H04L2012/6435 , H04L2012/644
摘要： A multi-node communications system is provided with communications protocol using both static (11, 12, 13, 18) (pre-determined) and dynamic (51, 52, 53...) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (11, 12, 13...) and the dynamic (51, 52, 53...) communication slots. Each node includes a synchronized time base 5 made up of consecutive timeslots (11, 12, 13..., 51, 52, 53...) . The timebase 5 has substantially the same error tolerance in each node. For static communication (10), a predetermined number of timeslots (20) are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots (60) are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern. Communication jitter is well defined and dealt with, and large oscillator drifts are compensated for.
摘要翻译：提供了具有使用静态（11,12,13,18）（预定）和动态（51,52,53 ...）（运行时确定的）连续通信时隙的通信协议的多节点通信系统用过的。该系统具有多个分布式通信节点，每个节点被布置用于在静态（11,12,13 ...）和动态（51,52,53 ...）期间与其他节点通信数据帧，通讯槽每个节点包括由连续时隙（11,12,13 ...，51,52,53 ...）组成的同步时基5。时基5在每个节点中具有基本上相同的误差容限。对于静态通信（10），对于每个静态通信时隙使用预定数量的时隙（20）。对于动态通信，动态分配数量的时隙（60）被用于每个动态通信时隙。以这种方式，在周期性循环通信模式中提供静态和动态媒体仲裁。通信抖动被很好地定义和处理，大的振荡器漂移被补偿。

5. 发明申请

WO2014080247A1 SYSTEM ON CHIP 审中-公开
标题翻译：芯片系统
公开(公告)号：WO2014080247A1
公开(公告)日：2014-05-30
申请号：PCT/IB2012/056669
申请日：2012-11-23
申请人： FREESCALE SEMICONDUCTOR, INC. , ROHLEDER, Michael , SINGER, Stefan , THANNER, Manfred
发明人： ROHLEDER, Michael , SINGER, Stefan , THANNER, Manfred
IPC分类号： G06F21/70 , G06F1/00
CPC分类号： G06F21/71 , G06F21/74 , G06F21/78 , G06F21/805 , G06F2213/0038
摘要： A system on chip (10) comprises one or more requestor unit (12), two or more responder units (14), two or more protection units (36), and a request analysis unit (34). Each of the responder units (14) comprises one or more responder element (15) and has associated with it one or more of the protection units (36). The request analysis unit (34) is arranged to receive from a requesting requestor unit (12) a request (with a set of request properties) for access to one or more target responder elements (15') among responder elements within a target responder unit among the responder units (14). The request analysis unit (34) is further arranged to determine relevant protection data on the basis of the request and on the basis of an authorization list (38), which comprises one or more entries, each at least specifying a group of one or more responder elements (15) and a set of access requirements for the group. The determining of the relevant protection data comprises, for each entry of the authorization list (38): taking the set of access requirements specified by the respective entry only into account if one or more of the target responder elements (15') are part of the group of responder elements (15) specified by the respective entry. The request analysis unit (34) is further arranged to provide the relevant protection data to one or more target protection unit(s) (36), the target protection unit(s) being the protection unit(s) associated with the responder unit(s), and located in a hierarchical path between the requesting requestor unit (12) requestor unit and the target responder unit. The target protection unit(s) (36) are arranged to perform a protective action for the target responder elements (15') on the basis of the relevant protection data.
摘要翻译：片上系统（10）包括一个或多个请求单元（12），两个或多个应答单元（14），两个或更多个保护单元（36）和请求分析单元（34）。响应器单元（14）中的每一个包括一个或多个应答器元件（15），并且与其相关联一个或多个保护单元（36）。请求分析单元（34）被布置为从请求请求者单元（12）接收用于访问目标响应器单元内的响应者元素中的一个或多个目标应答器元素（15'）的请求（具有一组请求属性）在响应单位（14）中。所述请求分析单元（34）还被布置为基于所述请求并且基于包括一个或多个条目的授权列表（38）来确定相关保护数据，所述授权列表（38）至少指定一个或多个响应者元素（15）和组的一组访问要求。相关保护数据的确定包括对于授权列表（38）的每个条目：仅当目标响应器元素（15'）中的一个或多个是由相应条目指定的响应者元素组（15）。所述请求分析单元（34）还被布置成将相关保护数据提供给一个或多个目标保护单元（36），所述目标保护单元是与应答单元相关联的保护单元（ s），并且位于请求请求单元（12）请求单元和目标应答单元之间的分层路径中。目标保护单元（36）被布置成基于相关保护数据对目标响应器元件（15'）执行保护动作。

6. 发明申请

WO2014177904A1 MEMORY CONTROLLER 审中-公开
标题翻译：内存控制器
公开(公告)号：WO2014177904A1
公开(公告)日：2014-11-06
申请号：PCT/IB2013/053385
申请日：2013-04-29
申请人： FREESCALE SEMICONDUCTOR, INC. , FRANK, Juergen , STAUDENMAIER, Michael , THANNER, Manfred
发明人： FRANK, Juergen , STAUDENMAIER, Michael , THANNER, Manfred
IPC分类号： G06F21/78 , G06F21/30 , G06F13/16
CPC分类号： G06F21/79 , G06F12/0246 , G06F12/1458 , G06F21/44 , G06F21/572 , G06F21/6218 , G06F21/64 , G06F2212/1052
摘要： A memory controller (10) used to verify authenticity of data (DATA) stored in a first memory unit (15). The memory controller (10) includes a secure memory unit (20) which stores a pre-stored value (PV) representative for the authenticity of the data (DATA) to be written in the first memory unit (15). The memory controller (10) further includes a processing system (25). The processing system (25) is configured to calculate a calculated value (CV) which is representative for the data (DATA) in the first memory unit (15) after a write cycle (WC). The calculation of the calculated value (CV) is triggered by the write cycle (WC). The processing system (25) further compares the calculated value (CV) with the pre-stored value (PV) in order to verify whether the data (DATA) stored in the first memory unit (15) after the write cycle (WC) has been altered in accordance with the authenticity. By comparing the calculated value (CV) with the pre-stored value (PV) authenticity of the data (DATA) stored in the first memory unit (15) after the write cycle (WC) is verified, thus preventing the memory controller (10) to continue operating in case the data (DATA) written to the first memory unit (15) is not anymore authentic.
摘要翻译：用于验证存储在第一存储器单元（15）中的数据（DATA）的真实性的存储器控制器（10）。存储器控制器（10）包括一个安全存储器单元（20），其存储代表要写入第一存储器单元（15）的数据（DATA）的真实性的预存储值（PV）。存储器控制器（10）还包括处理系统（25）。处理系统（25）被配置为在写周期（WC）之后计算代表第一存储器单元（15）中的数据（DATA）的计算值（CV）。计算值（CV）的计算由写周期（WC）触发。处理系统（25）进一步将计算出的值（CV）与预先存储的值（PV）进行比较，以验证在写周期（WC）之后存储在第一存储器单元（15）中的数据（DATA）是否具有根据真实性进行了修改。通过在验证写周期（WC）之后，将计算值（CV）与存储在第一存储器单元（15）中的数据（DATA）的预存值（PV）真实性进行比较，从而防止存储器控制器）在写入第一存储器单元（15）的数据（DATA）不再可靠的情况下继续操作。

7. 发明申请

WO2009153623A1 MEMORY SYSTEM WITH REDUNDANT DATA STORAGE AND ERROR CORRECTION 审中-公开
标题翻译：具有冗余数据存储和错误校正的存储器系统
公开(公告)号：WO2009153623A1
公开(公告)日：2009-12-23
申请号：PCT/IB2008/052447
申请日：2008-06-20
申请人： FREESCALE SEMICONDUCTOR, INC. , ROHLEDER, Michael , HAY, Gary , MUELLER, Stephan , THANNER, Manfred
发明人： ROHLEDER, Michael , HAY, Gary , MUELLER, Stephan , THANNER, Manfred
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G06F11/167 , G11C29/74 , G11C2029/0411
摘要： A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RA M routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from th e at least two RAM elements and provide an error indication signal to the RAM routing logic in re sponse thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of t he redundant data and the error indication signal.
摘要翻译：系统包括被布置为冗余地存储数据的至少两个随机存取存储器（RAM）元件。系统还包括RA M路由逻辑，其包括可操作地耦合到所述至少两个RAM元素的比较逻辑，并且被布置为比较与所述至少两个RAM元素读取的冗余数据，以及独立于所述RAM路由逻辑的检查和验证逻辑，至少两个RAM元件，并且被布置为附加地检测从至少两个RAM元件读取的冗余数据中的错误，并向RAM路由逻辑提供错误指示信号以对其进行响应。 RAM路由逻辑还包括选择逻辑，其被布置为基于冗余数据和错误指示信号的比较来动态地从至少两个RAM元素中的一个RAM元素中选择冗余数据。

8. 发明申请

WO2009090502A1 PROCESSOR BASED SYSTEM HAVING ECC BASED CHECK AND ACCESS VALIDATION INFORMATION MEANS 审中-公开
标题翻译：基于ECC的基于处理器的系统检查和访问验证信息手段
公开(公告)号：WO2009090502A1
公开(公告)日：2009-07-23
申请号：PCT/IB2008/050149
申请日：2008-01-16
申请人： FREESCALE SEMICONDUCTOR, INC. , ROHLEDER, Michael , HAY, Gary , MUELLER, Stephan , THANNER, Manfred
发明人： ROHLEDER, Michael , HAY, Gary , MUELLER, Stephan , THANNER, Manfred
IPC分类号： G06F11/00 , G06F12/14
CPC分类号： G06F11/1645 , G06F11/10 , G06F11/1654 , G06F2201/845
摘要： A system (100) comprises a first master element (110, 910); and at least one shared communication element (130, 940) arranged to operably couple the first master element (110, 910) to at least one slave element (140, 150, 170). The system (100) further comprises at least one validation element (180, 190, 960, 970, 980, 990) located on at least one further validation path (114, 124, 117) located between the first master element (110, 910) and the at least one slave element (140, 150, 170), wherein the at least one validation element (180, 190, 960, 970, 980, 990) is arranged to validate at least one of: at least one access request by the first master element (110, 910); and a response to an access request from the at least one slave element (140, 150, 170).
摘要翻译：系统（100）包括第一主元件（110,910）; 以及布置成可操作地将第一主元件（110,910）耦合到至少一个从属元件（140,150,170）的至少一个共享通信元件（130,940）。所述系统（100）还包括至少一个确定元件（180,190,960,970,980,990），位于所述第一主元件（110,910）之间的至少一个另外的验证路径（114,124,117）上，）和所述至少一个从属元件（140,150,170），其中所述至少一个验证元件（180,190,990,970,980,990）被布置成验证以下至少一个：至少一个访问请求通过第一主元件（110,910）; 以及对来自所述至少一个从属元件（140,150,170）的访问请求的响应。

9. 发明申请

WO2004051925A2 SYSTEM NODE AND METHOD FOR PROVIDING MEDIA ARBITRATION 审中-公开
标题翻译：用于提供媒体仲裁的系统节点和方法
公开(公告)号：WO2004051925A2
公开(公告)日：2004-06-17
申请号：PCT/EP2003/050868
申请日：2003-11-21
申请人： MOTOROLA INC , TEMPLE, Christopher , BOGENBERGER, Florian , RAUSCH, Mathias , THANNER, Manfred , WUERZ, Thomas , LINK, Leonard , POKORNY, Gregor
发明人： TEMPLE, Christopher , BOGENBERGER, Florian , RAUSCH, Mathias , THANNER, Manfred , WUERZ, Thomas , LINK, Leonard , POKORNY, Gregor
IPC分类号： H04L12/00
CPC分类号： H04L12/417 , H04L12/413 , H04L12/6418 , H04L2012/40241 , H04L2012/40273 , H04L2012/6435 , H04L2012/644
摘要： A multi-node communications system is provided with communications protocol using both static (11, 12, 13, 18) (pre-determined) and dynamic (51, 52, 53...) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (11, 12, 13...) and the dynamic (51, 52, 53...) communication slots. Each node includes a synchronized time base 5 made up of consecutive timeslots (11, 12, 13..., 51, 52, 53...) . The timebase 5 has substantially the same error tolerance in each node. For static communication (10), a predetermined number of timeslots (20) are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots (60) are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern. Communication jitter is well defined and dealt with, and large oscillator drifts are compensated for.
摘要翻译：提供了具有使用静态（11,12,13,18）（预定）和动态（51,52,53 ...）（运行时确定的）连续通信时隙的通信协议的多节点通信系统用过的。该系统具有多个分布式通信节点，每个节点被布置用于在静态（11,12,13 ...）和动态（51,52,53 ...）期间与其他节点通信数据帧，通讯槽每个节点包括由连续时隙（11,12,13 ...，51,52,53 ...）组成的同步时基5。时基5在每个节点中具有基本上相同的误差容限。对于静态通信（10），对于每个静态通信时隙使用预定数量的时隙（20）。对于动态通信，动态分配数量的时隙（60）被用于每个动态通信时隙。以这种方式，在周期性循环通信模式中提供静态和动态媒体仲裁。通信抖动被很好地定义和处理，大的振荡器漂移被补偿。

10. 发明申请

WO2015008114A1 ILLEGAL MESSAGE DESTROYER 审中-公开
标题翻译：非法消息破坏者
公开(公告)号：WO2015008114A1
公开(公告)日：2015-01-22
申请号：PCT/IB2013/055914
申请日：2013-07-18
申请人： FREESCALE SEMICONDUCTOR, INC. , FRANK, Juergen , STAUDENMAIER, Michael , THANNER, Manfred
发明人： FRANK, Juergen , STAUDENMAIER, Michael , THANNER, Manfred
IPC分类号： H04L12/22 , H04L9/00 , G06F21/00 , H04L12/58
CPC分类号： H04L63/1416 , G06F21/606 , H04L12/40032 , H04L12/40169 , H04L63/10 , H04L63/12 , H04L63/1466 , H04L2012/40215 , H04L2012/40273
摘要： A communication apparatus for preventing the broadcasting of unauthorised messages on a broadcast bus network, the communication apparatus comprising: - a first memory adapted to store first information; - a second memory adapted to store second information; - a monitoring unit adapted to: - monitor the bus for processing messages being broadcasted on the bus, and - output a third information and fourth information - a comparing unit adapted to compare the first information with the third information and the second information with the fourth information; and, - a message destroyer adapted to: when: - the first information matches with the third information, and - the second information does not match with the fourth information, causing the body of the current message to be altered while the current message is being broadcasted on the bus.
摘要翻译：一种用于防止在广播总线网络上广播未经授权的消息的通信装置，所述通信装置包括： - 适于存储第一信息的第一存储器; - 适于存储第二信息的第二存储器; - 监视单元，适于： - 监视总线以处理在总线上广播的消息，以及 - 输出第三信息和第四信息 - 适于将第一信息与第三信息和第二信息进行比较的比较单元，第四信息和第四信息信息; 以及 - 消息驱逐器，其适于：何时： - 所述第一信息与所述第三信息匹配，以及 - 所述第二信息与所述第四信息不匹配，导致当前消息正在被所述当前消息的正文被改变在公车上广播

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