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1. 发明申请

WO2010062555A1 PHYSICAL FORCE CAPACITIVE TOUCH SENSOR 审中-公开
标题翻译：物理电容触摸传感器
公开(公告)号：WO2010062555A1
公开(公告)日：2010-06-03
申请号：PCT/US2009/062054
申请日：2009-10-26
申请人： MICROCHIP TECHNOLOGY INCORPORATED , CURTIS, Keith , DUVENHAGE, Fanie
发明人： CURTIS, Keith , DUVENHAGE, Fanie
IPC分类号： G06F3/044 , G06F3/041
CPC分类号： G06F3/0414 , G06F3/044 , H03K17/975
摘要： A physical force capacitive touch sensor comprises a capacitive sensor element on a substrate, a physically deformable electrically insulating spacer over the capacitive sensor element, and a conductive plane over the physically deformable electrically insulating spacer that is substantially parallel to the capacitive sensor element. The conductive plane is connected to a power supply common and/or grounded to form a capacitor with the capacitive sensor element and for improved shielding of the capacitive sensor element from electrostatic disturbances and false triggering thereof. A protective cover may be placed over the conductive plane to act as an environmental seal for improved physical and weather protection, but is not essential to operation of the capacitive touch sensor.
摘要翻译：物理力电容式触摸传感器包括基板上的电容式传感器元件，电容式传感器元件上的可物理变形的电绝缘隔离物，以及基本上平行于电容式传感器元件的物理上可变形的电绝缘间隔物上的导电平面。导电平面连接到公共和/或接地的电源以与电容式传感器元件形成电容器，并且用于改善电容式传感器元件的屏蔽以免静电干扰和其错误触发。保护盖可以放置在导电平面上以用作环境密封件，以改善物理和天气保护，但对于电容式触摸传感器的操作来说不是必需的。

2. 发明申请

WO2012145511A3 CONFIGURABLE LOGIC CELLS 审中-公开
标题翻译：可配置逻辑电池
公开(公告)号：WO2012145511A3
公开(公告)日：2013-02-14
申请号：PCT/US2012034250
申请日：2012-04-19
申请人： MICROCHIP TECH INC , KILZER KEVIN LEE , STEEDMAN SEAN , ZDENEK JERROLD S , DELPORT VIVIEN , LUNDSTRUM ZEKE , DUVENHAGE FANIE
发明人： KILZER KEVIN LEE , STEEDMAN SEAN , ZDENEK JERROLD S , DELPORT VIVIEN , LUNDSTRUM ZEKE , DUVENHAGE FANIE
IPC分类号： G06F15/78
CPC分类号： H03K19/17708 , G06F15/7867
摘要： An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.
摘要翻译：根据权利要求的实施例的集成电路装置包括中央处理核心; 以及可操作地耦合到RISC CPU核心的多个外围设备。在一些实施例中，多个外围设备包括具有比集成电路设备上的输入 - 输出连接更多的输入的至少一个可配置逻辑单元外围设备。在一些实施例中，输入包括来自一个或多个集成电路子系统的一个或多个输入。

3. 发明申请

WO2012145505A1 SELECTING FOUR SIGNALS FROM SIXTEEN INPUTS 审中-公开
标题翻译：从第六代输入选择四个信号
公开(公告)号：WO2012145505A1
公开(公告)日：2012-10-26
申请号：PCT/US2012/034242
申请日：2012-04-19
申请人： MICROCHIP TECHNOLOGY INCORPORATED , KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
发明人： KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
IPC分类号： H03K19/173
CPC分类号： H03K19/1737 , H03K19/17744
摘要： An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to I multiplexer.
摘要翻译：一种用于从设备中的多个y信号中选择多个输入信号的装置具有具有多个n至1个多路复用器的交换矩阵，其中每个n至1多路复用器被分配给y个信号的n个的不同输入集合其中n到1个复用器中的每一个的每组输入信号的小于n个输入信号的子集也是另一个n到I多路复用器的输入信号的子集。

4. 发明申请

WO2012145578A1 CONFIGURABLE LOGIC CELLS 审中-公开
标题翻译：可配置逻辑电池
公开(公告)号：WO2012145578A1
公开(公告)日：2012-10-26
申请号：PCT/US2012/034367
申请日：2012-04-20
申请人： MICROCHIP TECHNOLOGY INCORPORATED , KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
发明人： KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
IPC分类号： H03K19/177
CPC分类号： G06F15/7871 , H03K19/177 , H03K19/17708
摘要： A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.
摘要翻译：处理器包括一个RISC CPU内核; 以及包括一个或多个可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为允许实时软件访问处理器的内部配置和信号路径。可配置逻辑单元外设可能具有实时配置控制。

5. 发明申请

WO2012145511A2 CONFIGURABLE LOGIC CELLS 审中-公开
标题翻译：可配置逻辑电池
公开(公告)号：WO2012145511A2
公开(公告)日：2012-10-26
申请号：PCT/US2012/034250
申请日：2012-04-19
申请人： MICROCHIP TECHNOLOGY INCORPORATED , KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
发明人： KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
IPC分类号： H03K19/173
CPC分类号： H03K19/17708 , G06F15/7867
摘要： An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.
摘要翻译：根据权利要求的实施例的集成电路装置包括中央处理核心; 以及可操作地耦合到RISC CPU核心的多个外围设备。在一些实施例中，多个外围设备包括至少一个可配置逻辑单元外围设备，其具有比集成电路设备上的输入 - 输出连接更多的输入。在一些实施例中，输入包括来自一个或多个集成电路子系统的一个或多个输入。

6. 发明申请

WO2012145508A1 A LOGIC DEVICE FOR COMBINING VARIOUS INTERRUPT SOURCES INTO A SINGLE INTERRUPT SOURCE AND VARIOUS SIGNAL SOURCES TO CONTROL DRIVE STRENGTH 审中-公开
标题翻译：用于将各种中断源组合成单个中断源和各种信号源以控制驱动强度的逻辑设备
公开(公告)号：WO2012145508A1
公开(公告)日：2012-10-26
申请号：PCT/US2012/034245
申请日：2012-04-19
申请人： MICROCHIP TECHNOLOGY INCORPORATED , KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
发明人： KILZER, Kevin, Lee , STEEDMAN, Sean , ZDENEK, Jerrold, S. , DELPORT, Vivien , LUNDSTRUM, Zeke , DUVENHAGE, Fanie
IPC分类号： H03K19/177
CPC分类号： H03K19/17712 , H03K19/17708
摘要： A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions.
摘要翻译：处理器包括RISC CPU内核和包括可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为将多个输入组合成单个输出。可配置逻辑单元可以被编程为用作多个预定逻辑功能之一。

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