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1. 发明申请

WO2008144579A3 FRACTIONAL-N SYNTHESIZED CHIRP GENERATOR 审中-公开
公开(公告)号：WO2008144579A3
公开(公告)日：2008-11-27
申请号：PCT/US2008/064003
申请日：2008-05-16
申请人： SIERRA MONOLITHICS, INC. , HORNBUCKLE, Craig, A.
发明人： HORNBUCKLE, Craig, A.
IPC分类号： H03K5/01
摘要： A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

2. 发明申请

WO2008066694A2 ENCODING AND DECODING ARCHITECTURE AND METHOD FOR PIPELINING ENCODED DATA OR PIPELINING WITH A LOOK-AHEAD STRATEGY 审中-公开
标题翻译：编码和解码结构和方法用于管理编码数据或管道与前瞻性策略
公开(公告)号：WO2008066694A2
公开(公告)日：2008-06-05
申请号：PCT/US2007/023759
申请日：2007-11-13
申请人： SIERRA MONOLITHICS INC. , STEIDL, Samuel, A. , CURRAN, Peter, F.
发明人： STEIDL, Samuel, A. , CURRAN, Peter, F.
IPC分类号： H04J14/08 , H04B10/12
CPC分类号： H04L27/2075
摘要： An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
摘要翻译：编码和/或解码通信系统包括成帧器接口，编码器，多路复用器，输出驱动器和时钟倍增器单元（CMU）。编码器包括输入锁存电路级; 输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的中间锁存电路级，中间锁存电路级耦合到输入锁存电路级和输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的多个编码逻辑电路级，多个编码逻辑电路级中的最后一个与输出锁存电路级放置并耦合到输出锁存电路级; 以及输出锁存电路级与多个编码逻辑电路级中的最后一个之间的反馈。

3. 发明申请

WO2008144579A2 FRACTIONAL-N SYNTHESIZED CHIRP GENERATOR 审中-公开
标题翻译：分类合成CHIRP发生器
公开(公告)号：WO2008144579A2
公开(公告)日：2008-11-27
申请号：PCT/US2008064003
申请日：2008-05-16
申请人： SIERRA MONOLITHICS INC , HORNBUCKLE CRAIG A
发明人： HORNBUCKLE CRAIG A
IPC分类号： H03L7/085
CPC分类号： H03L7/1976
摘要： A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.
摘要翻译：分数N合成啁啾发生器包括分数N合成器和数字斜坡合成器。分数N合成器具有频率合成器和Σ-Δ调制器模块。分数N合成器被配置为接收参考频率输入信号和频率控制值。分数N合成器被配置为以确定的方式将参考频率信号和频率控制值转换成啁啾射频（RF）输出信号。数字斜坡合成器被配置为接收参考频率输入信号并被配置为利用参考频率输入信号产生频率控制值。数字斜坡合成器还被配置为向小数N合成器提供频率控制值。频率控制值随时间变化。

4. 发明申请

WO2008066694A3 ENCODING AND DECODING ARCHITECTURE AND METHOD FOR PIPELINING ENCODED DATA OR PIPELINING WITH A LOOK-AHEAD STRATEGY 审中-公开
标题翻译：编码和解码结构和方法用于管理编码数据或管道与前瞻性策略
公开(公告)号：WO2008066694A3
公开(公告)日：2009-04-09
申请号：PCT/US2007023759
申请日：2007-11-13
申请人： SIERRA MONOLITHICS INC , STEIDL SAMUEL A , CURRAN PETER F
发明人： STEIDL SAMUEL A , CURRAN PETER F
IPC分类号： H04L12/26
CPC分类号： H04L27/2075
摘要： An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
摘要翻译：编码和/或解码通信系统包括成帧器接口，编码器，多路复用器，输出驱动器和时钟倍增器单元（CMU）。编码器包括输入锁存电路级; 输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的中间锁存电路级，中间锁存电路级耦合到输入锁存电路级和输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的多个编码逻辑电路级，多个编码逻辑电路级中的最后一个与输出锁存电路级放置并耦合到输出锁存电路级; 以及输出锁存电路级与多个编码逻辑电路级中的最后一个之间的反馈。

5. 发明申请

WO2005092027A2 MULTI-CHANNEL FILTERING SYSTEM FOR TRANSCEIVER ARCHITECTURES 审中-公开
标题翻译：用于收发器架构的多通道滤波系统
公开(公告)号：WO2005092027A2
公开(公告)日：2005-10-06
申请号：PCT/US2005009343
申请日：2005-03-21
申请人： SIERRA MONOLITHICS INC , ROWE DAVID A , HORNBUCKLE CRAIG A , POPE MATTHEW D
发明人： ROWE DAVID A , HORNBUCKLE CRAIG A , POPE MATTHEW D
IPC分类号： H04B1/04 , H04B1/10 , H04B1/28 , H04B1/38 , H04B1/40 , H04B1/44
CPC分类号： H04B1/28 , H04B1/406
摘要： A multi-channel filtering system for use with a transceiver includes a front-end multi-pole, multi-throw switch, a back-end multi-pole, multi-throw switch, and a plurality of filters. The front-end switch includes a receive pole, a transmit pole, and a plurality of switch throws. The back-end switch also includes a receive pole, a transmit pole, and a plurality of switch throws. Each of the plurality of filters has first and second ports, each first port coupled to one of the switch throws of the front-end switch, and each second port coupled to one of the switch throws of the back-end switch. Using this configuration, filters of differing bandwidths can be switched in during signal reception and/or transmission, thereby tailoring the communication rate to the particular conditions.
摘要翻译：用于收发器的多通道滤波系统包括前端多极，多掷开关，后端多极，多掷开关和多个滤波器。前端开关包括接收极，发射极和多个开关掷。后端开关还包括接收极，发射极和多个开关掷。多个滤波器中的每一个具有第一和第二端口，每个第一端口耦合到前端开关的开关引脚之一，并且每个第二端口耦合到后端开关的一个开关引脚。使用这种配置，可以在信号接收和/或传输期间切换不同带宽的滤波器，从而根据特定条件调整通信速率。

6. 发明申请

WO2003046983A1 CONNECTION PACKAGE FOR HIGH-SPEED INTEGRATED CIRCUIT 审中-公开
标题翻译：高速集成电路的连接封装
公开(公告)号：WO2003046983A1
公开(公告)日：2003-06-05
申请号：PCT/US2002/037586
申请日：2002-11-21
申请人： SIERRA MONOLITHICS, INC.
发明人： LAO, Binneg, Y. , CHEN, William, W. , ROWE, David, A. , KIM, Inho
IPC分类号： H01L23/48
CPC分类号： H01L24/49 , H01L23/49816 , H01L23/66 , H01L24/48 , H01L2223/6616 , H01L2223/6622 , H01L2223/6627 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01039 , H01L2924/01055 , H01L2924/01076 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15173 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/1903 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package (1120) includes a substrate having microstrips (e.g. 1105 and 1106) for communicating signals between IC pads and external terminals. A pairof differential microstrips are positioned closer to each other near the IC pads and create capacitive coupling.
摘要翻译：集成电路封装（1120）包括具有用于在IC焊盘和外部端子之间传送信号的微带（例如1105和1106）的衬底。 pairof微型差动微带在IC焊盘附近定位得更靠近，并产生电容耦合。

7. 发明申请

WO2003021773A1 ULTRA-WIDEBAND POWER AMPLIFIER MODULE APPARATUS AND METHOD FOR OPTICAL AND ELECTRONIC COMMUNICATIONS 审中-公开
标题翻译：超宽带功率放大器模块设备和光电通信方法
公开(公告)号：WO2003021773A1
公开(公告)日：2003-03-13
申请号：PCT/US2002/026634
申请日：2002-08-26
申请人： SIERRA MONOLITHICS, INC.
发明人： TAM, Alan, K. , LAO, Binneg, Y.
IPC分类号： H03G5/16
CPC分类号： H03F3/602
摘要： A broadband power amplifier module for high bit-rate SONET/SDH transmission channels, such as OC-192 and OC-768 applications. The power amplifier module, or also frequently referred to as modulator driver module, comprises amplifiers (410, 415) connected in series to amplify an input signal.(405) A bias tee circuit (440, 417) is incorporated into the power amplifier module by connecting a conical shape inductor (440) between the output stage of the amplifiers and the supply voltage (Vdd) and connecting a pair of blocking capacitors (407, 412, 417) also at the output stage of the amplifiers. The conical shape inductor is adapted to provide high impedance over the entire approaching or exceeding the bandwidth frequency. A power detection circuit (430) can also be incorporated into the power amplifier module at the output stage of the amplifiers.
摘要翻译：用于高比特率SONET / SDH传输通道的宽带功率放大器模块，如OC-192和OC-768应用。功率放大器模块，或者也被称为调制器驱动器模块，包括串联连接的放大器（410,415）以放大输入信号。（405）偏置三通电路（440,417）被并入功率放大器模块通过在放大器的输出级与电源电压（Vdd）之间连接圆锥形电感器（440），并在放大器的输出级连接一对阻塞电容器（407,412,417）。圆锥形电感器适于在整个接近或超过带宽频率时提供高阻抗。功率检测电路（430）也可以在放大器的输出级并入功率放大器模块中。

8. 发明申请

WO2009036390A1 HIGH-SPEED SERIALIZER, RELATED COMPONENTS, SYSTEMS AND METHODS 审中-公开
标题翻译：高速串行程序，相关组件，系统和方法
公开(公告)号：WO2009036390A1
公开(公告)日：2009-03-19
申请号：PCT/US2008/076313
申请日：2008-09-12
申请人： SIERRA MONOLITHICS, INC. , HORNBUCKLE, Craig A. , ROWE, David A.
发明人： HORNBUCKLE, Craig A. , ROWE, David A.
IPC分类号： H04J14/08
CPC分类号： H04J3/047 , H04B10/532 , H04B10/5561 , H04J3/0691 , H04J14/06 , H04L27/2067 , H04L27/36
摘要： A communication system includes a multiplexer configured to multiplex a first set of data channels into a first data channel and to multiplex a second set of data channels into a second data channel, and a delay adjuster configured to adjustably delay the first data channel based on a delay adjust command. The communication system also includes a first amplifier configured to amplify the delayed first channel into a first output data channel, and a second amplifier configured to amplify the second data channel into a second output data channel. The communication system further includes a first driver configured to convert the first output data channel into a first drive signal to drive an optical modulator, and a second driver configured to convert the second output data channel into a second drive signal to drive the optical modulator.
摘要翻译：通信系统包括多路复用器，其被配置为将第一组数据信道多路复用到第一数据信道中，并将第二组数据信道复用到第二数据信道中;以及延迟调整器，被配置为可调节地延迟第一数据信道，延时调整指令。通信系统还包括第一放大器，其被配置为将延迟的第一信道放大为第一输出数据信道，以及第二放大器，被配置为将第二数据信道放大为第二输出数据信道。通信系统还包括配置成将第一输出数据信道转换为第一驱动信号以驱动光调制器的第一驱动器，以及被配置为将第二输出数据信道转换为第二驱动信号以驱动光调制器的第二驱动器。

9. 发明申请

WO03046983A8 CONNECTION PACKAGE FOR HIGH-SPEED INTEGRATED CIRCUIT 审中-公开
标题翻译：高速集成电路的连接封装
公开(公告)号：WO03046983A8
公开(公告)日：2004-04-22
申请号：PCT/US0237586
申请日：2002-11-21
申请人： SIERRA MONOLITHICS INC
发明人： LAO BINNEG Y , CHEN WILLIAM W , ROWE DAVID A , KIM INHO
IPC分类号： H01L23/498 , H01L23/66 , H01L23/48 , H03H7/38
CPC分类号： H01L24/49 , H01L23/49816 , H01L23/66 , H01L24/48 , H01L2223/6616 , H01L2223/6622 , H01L2223/6627 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01039 , H01L2924/01055 , H01L2924/01076 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15173 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/1903 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package (1120) includes a substrate having microstrips (e.g. 1105 and 1106) for communicating signals between IC pads and external terminals. A pairof differential microstrips are positioned closer to each other near the IC pads and create capacitive coupling.
摘要翻译：集成电路封装（1120）包括具有用于在IC焊盘和外部端子之间传送信号的微带（例如1105和1106）的衬底。 pairof微型差动微带在IC焊盘附近定位得更靠近，并产生电容耦合。

10. 发明申请

WO2003085872A3 QUADRATURE RING OSCILLATOR 审中-公开
公开(公告)号：WO2003085872A3
公开(公告)日：2003-10-16
申请号：PCT/US2003/010199
申请日：2003-04-02
申请人： SIERRA MONOLITHICS, INC.
发明人： KRAWCZYK, Thomas, W., Jr. , ROWE, David, A.
IPC分类号： H03B5/00
摘要： A quadrature LC ring oscillator may use two stages of LC oscillators and variable mixers (810,830) to provide consistent oscillation. One stage of the ring oscillator comprises a first resonating element having input and output and a first variable summer (830) with L and P inputs and an output. The output of the first variable summer is connected to the input of the first resonating element. A second stage of the LC ring oscillator comprises a second resonating element, which has an input and output, with its output being connected to the P input of the first variable summer. An inverter is used to produce an inverted signal of the output of the first resonating element. This stage also comprises a second variable summer (810) having L and P inputs and an output, with its output connected to the input of the second resonating element.

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