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1. 发明申请

WO2013148196A1 METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW 审中-公开
标题翻译： ONO集成到逻辑CMOS流的方法
公开(公告)号：WO2013148196A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/030874
申请日：2013-03-13
申请人： CYPRESS SEMICONDUCTOR CORPORATION , RAMKUMAR, Krishnaswamy , JIN, Bo , JENNE, Fredrick
发明人： RAMKUMAR, Krishnaswamy , JIN, Bo , JENNE, Fredrick
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11573 , H01L27/11582 , H01L29/513 , H01L29/518 , H01L29/66833
摘要： An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域之上形成MOS器件的焊盘电介质层; 从半导体材料的薄膜形成存储器件的沟道，该半导体材料的薄膜覆盖在衬底的第二区域上方的表面，所述通道连接存储器件的源极和漏极; 形成覆盖在第二区域上方的通道上的图案化电介质堆叠，所述图案化电介质叠层包括隧道层，电荷俘获层和牺牲顶层; 同时从衬底的第二区域去除牺牲顶层，以及从衬底的第一区域去除焊盘介电层; 并且同时在衬底的第一区域上方形成栅极电介质层，并且在电荷俘获层上方形成阻挡电介质层。

2. 发明申请

WO2013148112A1 SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER 审中-公开
标题翻译： SONOS堆叠分离硝酸盐存储层
公开(公告)号：WO2013148112A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/029784
申请日：2013-03-08
申请人： CYPRESS SEMICONDUCTOR CORPORATION , JENNE, Fredrick , RAMKUMAR, Krishnaswamy
发明人： JENNE, Fredrick , RAMKUMAR, Krishnaswamy
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28282 , H01L27/11582 , H01L29/0673 , H01L29/0676 , H01L29/42348 , H01L29/513 , H01L29/518 , H01L29/66439 , H01L29/66833 , H01L29/775 , H01L29/785 , H01L29/7926
摘要： Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.
摘要翻译：描述了包括分离电荷捕获区域的非平面存储器件及其形成方法的实施例。通常，该器件包括：由覆盖存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 分离电荷捕获区域，覆盖隧道氧化物，分离电荷捕获区域包括底部电荷捕获层，其包含更接近隧道氧化物的氮化物，以及顶部电荷捕获层，其中底部电荷捕获层被分离从顶部的电荷捕获层通过包含氧化物的薄的抗隧道层。还公开了其他实施例。

3. 发明申请

WO2009014527A1 DEUTERATED FILM ENCAPSULATION OF NONVOLATILE CHARGE TRAP MEMORY DEVICE 审中-公开
标题翻译：非挥发性电荷捕获存储器件的检测膜封装
公开(公告)号：WO2009014527A1
公开(公告)日：2009-01-29
申请号：PCT/US2007/020954
申请日：2007-09-28
申请人： CYPRESS SEMICONDUCTOR CORPORATION , RAMKUMAR, Krishnaswamy , JENNE, Fredrick, B. , KOUTNY, William
发明人： RAMKUMAR, Krishnaswamy , JENNE, Fredrick, B. , KOUTNY, William
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/4234 , H01L29/511 , H01L29/792
摘要： A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.
摘要翻译：具有充电阱的氘钝化的非挥发性电荷陷阱存储器件及其制造方法。氘代栅极层，氘化栅极覆盖层和氘代间隔物被采用各种组合，以将器件与邻近栅极堆叠内的界面的氘源以及可能存在阱的栅极堆叠的表面封装。

4. 发明申请

WO2008147529A1 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES 审中-公开
标题翻译：非挥发性电荷捕获存储器件和逻辑CMOS器件的集成
公开(公告)号：WO2008147529A1
公开(公告)日：2008-12-04
申请号：PCT/US2008/006597
申请日：2008-05-23
申请人： CYPRESS SEMICONDUCTOR CORPORATION , RAMKUMAR, Krishnaswamy , KAPRE, Ravindra , WARREN, Jeremy
发明人： RAMKUMAR, Krishnaswamy , KAPRE, Ravindra , WARREN, Jeremy
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7836 , H01L29/7843
摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SCl cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。可以避免HF预净化和SCl清洗以提高非挥发性电荷陷阱存储器件的阻挡层的质量。在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

5. 发明申请

WO2008147383A1 NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING <100> CRYSTAL PLANE CHANNEL ORIENTATION 审中-公开
标题翻译：具有<100>水晶平面通道定向的非挥发性电荷捕获存储器件
公开(公告)号：WO2008147383A1
公开(公告)日：2008-12-04
申请号：PCT/US2007/020956
申请日：2007-09-28
申请人： CYPRESS SEMICONDUCTOR CORPORATION , POLISHCHUK, Igor , LEVY, Sagy , RAMKUMAR, Krishnaswamy
发明人： POLISHCHUK, Igor , LEVY, Sagy , RAMKUMAR, Krishnaswamy
IPC分类号： H01L21/336 , H01L21/00
CPC分类号： H01L29/792 , H01L21/28123 , H01L21/28167 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/045 , H01L29/42324
摘要： A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.
摘要翻译：描述了一种非易失性电荷陷阱存储器件及其形成方法。该器件包括具有<100>晶面取向的沟道长度的沟道区。沟道区域位于一对源极区和漏极区之间，栅极堆叠设置在沟道区的上方。

6. 发明申请

WO2007092551A2 STRESS LINER FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路应力衬片
公开(公告)号：WO2007092551A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/003352
申请日：2007-02-07
申请人： CYPRESS SEMICONDUCTOR CORPORATION , POLISHCHUK, Igor , RAMKUMAR, Krishnaswamy , LEVY, Sagy Levy
发明人： POLISHCHUK, Igor , RAMKUMAR, Krishnaswamy , LEVY, Sagy Levy
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： In one embodiment, a self-aligned contact (SAC) trench structure (412) is formed through a dielectric layer (410) to expose an active region (404) of a MOS transistor. The SAC trench structure (412) not only exposes the active region (404) for electrical connection but also removes portions of a stress liner (409) over the active region (404). This leaves the stress liner (409) mostly on the sidewall and top of the gate (510) of the MOS transistor. Removing portions of the stress liner (409) over the active region substantially removes the lateral component of the strain imparted by the stress liner (409) on the substrate (402), allowing for improved drive current without substantially degrading a complementary MOS transistor.
摘要翻译：在一个实施例中，自对准接触（SAC）沟槽结构（412）通过电介质层（410）形成以暴露MOS晶体管的有源区（404）。 SAC沟槽结构（412）不仅暴露用于电连接的有源区（404），而且还去除有源区（404）上的应力衬垫（409）的部分。这使得应力衬垫（409）主要在MOS晶体管的栅极（510）的侧壁和顶部上。在有源区上移除应力衬垫（409）的部分基本上去除了由衬底（402）上的应力衬垫（409）施加的应变的侧向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

7. 发明申请

WO2014008160A2 SONOS ONO STACK SCALING 审中-公开
公开(公告)号：WO2014008160A2
公开(公告)日：2014-01-09
申请号：PCT/US2013/048874
申请日：2013-07-01
申请人： CYPRESS SEMICONDUCTOR CORPORATION , JENNE, Fredrick , LEVY, Sagy , RAMKUMAR, Krishnaswamy
发明人： JENNE, Fredrick , LEVY, Sagy , RAMKUMAR, Krishnaswamy
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/792 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C16/3468 , G11C16/349 , H01L21/28282 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/7926
摘要： A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygenlean second layer.
摘要翻译：提供了一种缩放非易失性俘获电荷存储器件及其制造的器件的方法。在一个实施例中，该方法包括形成包括电连接衬底中的源极区域和漏极区域的多晶硅沟道区域。通过氧化衬底以在沟道区域上的衬底上形成隧穿层以形成氧化膜并氮化氧化膜。在隧道层上形成包含富氧的第一层和无氧的第二层的多层电荷俘获层，以及沉积在多层电荷俘获层上的阻挡层。在一个实施方案中，该方法还包括稀释的湿氧化以致致密的沉积的阻塞氧化物并氧化一部分氧气第二层。

8. 发明申请

WO2005031833A1 OXIDE-NITRIDE STACK GATE DIELECTRIC 审中-公开
标题翻译：氧化物 - 氮化物堆积电介质
公开(公告)号：WO2005031833A1
公开(公告)日：2005-04-07
申请号：PCT/US2004/031541
申请日：2004-09-24
申请人： CYPRESS SEMICONDUCTOR CORPORATION , RAMKUMAR, Krishnaswamy , NARAYANAN, Sundar
发明人： RAMKUMAR, Krishnaswamy , NARAYANAN, Sundar
IPC分类号： H01L21/28
CPC分类号： H01L21/28185 , H01L21/28061 , H01L21/28202 , H01L21/28211 , H01L21/28247 , H01L21/3143 , H01L21/324 , H01L29/513 , H01L29/518 , H04L25/03159 , H04L2025/03414 , H04L2025/03496 , H04L2025/03522
摘要： A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.
摘要翻译：制造半导体结构的方法包括在衬底上形成氧化物层; 在氧化物层上形成氮化硅层; 在NO中退火层; 并在氨中退火层。氧化物层和氮化硅层的等效氧化物厚度在一起为至多25埃。

9. 发明申请

WO2004095525A2 GATE ELECTRODE FOR MOS TRANSISTORS 审中-公开
标题翻译： MOS晶体管的栅极电极
公开(公告)号：WO2004095525A2
公开(公告)日：2004-11-04
申请号：PCT/US2004/003441
申请日：2004-02-04
申请人： CYPRESS SEMICONDUCTOR CORPORATION , BLOSSE, Alain , RAMKUMAR, Krishnaswamy , GOPALAN, Prabhuram
发明人： BLOSSE, Alain , RAMKUMAR, Krishnaswamy , GOPALAN, Prabhuram
IPC分类号： H01L
CPC分类号： H01L29/4941 , H01L21/28052 , H01L21/324 , H01L21/3247 , H01L29/78
摘要： In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer (112'), forming a metal stack (110') over the silicon layer (112'), and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.
摘要翻译：在一个实施例中，通过对硅层（112'）进行第一热处理，在硅层（112'）上方形成金属叠层（110'），并对第一热处理金属堆栈。第一热处理可以是快速热退火步骤，而第二热处理可以是快速热氮化步骤。所得到的栅极在硅层和金属堆叠之间表现出相对低的界面接触电阻，因此可以有利地用于高速器件中。

10. 发明申请

WO2013148393A1 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES 审中-公开
标题翻译：非挥发性电荷捕获存储器件和逻辑CMOS器件的集成
公开(公告)号：WO2013148393A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/032777
申请日：2013-03-18
申请人： CYPRESS SEMICONDUCTOR CORPORATION , RAMKUMAR, Krishnaswamy , JENNE, Fredrick , LEVY, Sagy
发明人： RAMKUMAR, Krishnaswamy , JENNE, Fredrick , LEVY, Sagy
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28282 , H01L27/11573 , H01L29/0676 , H01L29/665 , H01L29/66833 , H01L29/7833 , H01L29/7926
摘要： An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

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