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1. 发明申请

WO2009103048A4 DUAL PHOTO-DIODE CMOS PIXELS 审中-公开
标题翻译：双光二极管CMOS像素
公开(公告)号：WO2009103048A4
公开(公告)日：2009-10-22
申请号：PCT/US2009034211
申请日：2009-02-16
申请人： QUANTUM SEMICONDUCTOR LLC
发明人： AUGUSTO CARLOS
IPC分类号： H01L27/146
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L27/14647
摘要： The present invention provides a method of forming CMOS pixels, with the light-sensing region comprising vertically aligned dual photo-diodes, in which the bottom photo-diode is formed either by a well-to-substrate junction, or by a deep-well-to-substrate junction, wherein said well and deep-well are independently biased from surrounding wells and deep-wells of the same polarity. Said independently biased well is a common region to the top and bottom photo-diodes and overlaps the source/drain region of a MOSFET formed on a well with the opposite polarity, that of the substrate. The photo-diodes can be electrically connected in parallel, or the top photo- diode can be biased separately from the bottom photo-diode, said bias can be such that avalanche mode operation is possible, including the single-photon detection (Geiger) mode.
摘要翻译：本发明提供了一种形成CMOS像素的方法，其中光敏区包括垂直对准的双光电二极管，其中底部光电二极管由阱到衬底结或深阱形成其中所述阱和深阱独立地偏离相同极性的周围阱和深阱。所述独立偏置的阱是顶部和底部光电二极管的共同区域，并且与阱上形成的MOSFET的源极/漏极区域以与衬底的极性相反的极性重叠。光电二极管可以并联电连接，或者顶部光电二极管可以与底部光电二极管分开偏置，所述偏置可以使得可以进行雪崩模式操作，包括单光子检测（盖格）模式。

2. 发明申请

WO2009030980A3 PHOTONIC VIA WAVEGUIDES FOR IMAGE SENSOR 审中-公开
标题翻译：用于图像传感器的波长的光电子
公开(公告)号：WO2009030980A3
公开(公告)日：2009-07-02
申请号：PCT/IB2007004682
申请日：2007-09-06
申请人： QUANTUM SEMICONDUCTOR LLC , AUGUSTO CARLOS J R P
发明人： AUGUSTO CARLOS J R P
IPC分类号： H01L27/146 , G02B6/122 , H01L31/0232
CPC分类号： G02B6/1225 , G02B6/08 , G02B6/12 , G02B6/4249 , G02B6/4298 , G02B6/43 , G02B2006/12166 , G02B2006/12176 , H01L27/14621 , H01L27/14629 , H01L27/14636 , H01L27/14685 , H01L31/0232
摘要： Photonic passive structure to couple and guide light between photonic active devices (101), such as photo-diodes, light emitting devices and light-valves, which may be arranged into 2D arrays, and the top of the metallization layer stack (110,111,112) interconnecting said devices, with said photonic passive structure comprising a hole (116) between the near surface of said photonic active Ndevices and the top of said metallization stack, said hole being filled with a dielectric (113) having embedded metal films (117) and in which the embedded metal thin films are connected to a planar perforated metal film (123,124) formed on top of the metallization stack.
摘要翻译：可以布置成2D阵列的光子二极管，发光器件和光阀之间的光子有源器件（101）耦合和引导光的光子无源结构以及互连的金属化层堆叠（110,111,112）的顶部所述器件具有所述光子被动结构，其包括在所述光子活性Ndevices的近表面和所述金属化堆叠的顶部之间的孔（116），所述孔填充有具有嵌入金属膜（117）的电介质（113）其中嵌入的金属薄膜连接到形成在金属化叠层顶部上的平面穿孔金属膜（123,124）。

3. 发明申请

WO2004054001A3 CMOS IMAGE SENSOR 审中-公开
标题翻译： CMOS图像传感器
公开(公告)号：WO2004054001A3
公开(公告)日：2004-08-12
申请号：PCT/EP0313953
申请日：2003-12-09
申请人： QUANTUM SEMICONDUCTOR LLC , AUGUSTO CARLOS J R P
发明人： AUGUSTO CARLOS J R P
IPC分类号： G02B5/18 , G02B5/20 , H01L27/12 , H01L27/14 , H01L27/146 , H01L31/0216 , H01L31/0232 , H01L31/105
CPC分类号： H01L27/14609 , G02B1/005 , G02B5/008 , G02B5/201 , G02B5/208 , H01L27/12 , H01L27/14618 , H01L27/14621 , H01L27/14625 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/105 , H01L2924/0002 , H01L2924/00
摘要： Light sensing devices are monolithically integrates with CMOS devices on Thin-Film Silicon-On-Insulator (TF-SOI) or Thin-Film Germanium-On-Insulator (TF-GeOI) substrates. Photodiode active layers are expitaxially grown on the front-side of the substrate and after full processing of the front-side of the substrate, the substrate material is removed under the buried insulator (buried oxide). Monolithically integrated structures are then fabricated on the back of the buried oxide. The back-side is then bonded to a new substrate that is transparent to the wavelengths of interest. For example, quartz, sapphire, glass or plastic, are suitable for the visible range. Back-side illumination of the sensor matrix is thereby allowed, with light traveling through the structures fabricated on the back of the substrate, opposite to the side on which CMOS is made.
摘要翻译：光感测装置与薄膜绝缘体上硅（TF-SOI）或薄膜绝缘体上（SOI-on-Insulator）（TF-GeOI）衬底上的CMOS器件单片集成。光电二极管有源层外延生长在基板的正面，在基板的正面完全处理之后，在掩埋绝缘体（掩埋氧化物）下去除基板材料。然后在掩埋氧化物的背面制造单片整体结构。然后将背面粘合到对感兴趣的波长透明的新基底。例如，石英，蓝宝石，玻璃或塑料，适用于可见光范围。从而允许传感器矩阵的背面照明，其中光穿过制造在衬底背面的结构，与制造CMOS的一侧相反。

4. 发明申请

WO2004027879A3 LIGHT-SENSING DEVICE 审中-公开
标题翻译：感光装置
公开(公告)号：WO2004027879A3
公开(公告)日：2004-04-29
申请号：PCT/EP0310346
申请日：2003-09-15
申请人： QUANTUM SEMICONDUCTOR LLC , AUGUSTO CARLOS J R P
发明人： AUGUSTO CARLOS J R P
IPC分类号： H01L27/02 , H01L27/144 , H01L27/146 , H01L31/00 , H01L31/0232 , H01L31/0328 , H01L31/10 , H01L31/107
CPC分类号： H01L27/14669 , H01L27/14609 , H01L27/14625 , H01L27/14643 , H01L27/14665 , H01L31/0232 , H01L31/107 , H01L31/1075
摘要： A method of fabricating light-sensing devices including photodiodes monolithically integrated with CMOS devices. Several types of photodiode devices (PIN, HIP) are epitaxially grown in one single step on active areas implanted in a common semiconductor substrate, the active areas having defined polarities. The epitaxially grown layers for the photodiode devices may be either undoped or in-situ doped with profiles suitable for their respective operation. With appropriate choice of substrate materials, device layers and heterojunction engineering and process architecture, it is possible to fabricate siliconbased and germanium-based multi-spectral sensors that can deliver pixel density and cost of fabrication comparable to the state of the art CCDs and CMOS image sensors. The method can be implemented with epitaxially deposited films on the following substrates: Silicon Bulk, Thick-Film and Thin-Film Silicon-On-Insulator (SOI), Germanium Bulk, Thick-Film and Thin-Film Germanium-On-Insulator (GeOI).
摘要翻译：一种制造包括与CMOS器件单片集成的光电二极管的光感测装置的方法。多个类型的光电二极管器件（PIN，HIP）在植入公共半导体衬底的有源区域的一个步骤中外延生长，有源区域具有确定的极性。用于光电二极管器件的外延生长层可以是未掺杂的或原位掺杂的，适用于它们各自的操作。通过适当选择衬底材料，器件层和异质结工程和工艺架构，可以制造基于硅和锗的多光谱传感器，可以提供与现有技术的CCD和CMOS图像相当的像素密度和制造成本传感器。该方法可以在以下基板上用外延沉积膜实现：硅体积，厚膜和薄膜绝缘体上硅（SOI），锗体积，厚膜和薄膜绝缘体（GeOI ）。

5. 发明申请

WO2015042610A2 SUPERLATTICE MATERIALS AND APPLICATIONS 审中-公开
标题翻译：超级材料和应用
公开(公告)号：WO2015042610A2
公开(公告)日：2015-03-26
申请号：PCT/US2014/057066
申请日：2014-09-23
申请人： QUANTUM SEMICONDUCTOR LLC
发明人： AUGUSTO, Carlos, Jorge R.P
IPC分类号： H01L29/68
CPC分类号： H01L29/155 , H01L27/1203 , H01L27/146 , H01L27/1461 , H01L27/14612 , H01L27/1462 , H01L29/045 , H01L29/0649 , H01L29/151 , H01L29/161 , H01L29/165 , H01L29/68 , H01L29/7371 , H01L29/78 , H01L29/7833 , H01L31/035236 , H01L31/101 , H01L31/1812 , Y02E10/50
摘要： A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.
摘要翻译：包括第IV族元素的超晶格细胞重复多次以形成超晶格。每个超晶格单元具有彼此平行的多个有序原子平面。超晶格中的至少两个原子平面具有不同的化学组成。超晶格电池中的一个或多个原子平面中的一个或多个选自碳，锡和铅的组分。这些超晶格产生各种应用，包括但不限于晶体管，光传感器和光源。

6. 发明申请

WO2009136285A2 PIXEL CIRCUITRY FOR ULTRA WIDE DYNAMIC RANGE 审中-公开
标题翻译：超声波动态范围的像素电路
公开(公告)号：WO2009136285A2
公开(公告)日：2009-11-12
申请号：PCT/IB2009/005755
申请日：2009-04-16
申请人： QUANTUM SEMICONDUCTOR LLC , AUGUSTO, Carlos
发明人： AUGUSTO, Carlos
IPC分类号： H04N5/355
CPC分类号： H04N5/35518 , H01L27/14609
摘要： The pixel circuitry of the invention enables light sensing through a photo-current mode with logarithmic compression and through accumulation of charges, with a seamless transition between the modes that depends only on the light signal strength, and not on external control signals. The pixel circuitry of the invention also allows said photo-current mode for a pixel matrix operated in the electronic global shutter mode, provides anti-blooming capability, and allows for sharing of certain pixel circuit elements between a plurality of pixels.
摘要翻译：本发明的像素电路通过具有对数压缩和通过电荷积累的光电流模式实现光感测，其中仅依赖于光信号强度的模式之间的无缝转换而不是外部控制信号。本发明的像素电路还允许在电子全局快门模式下操作的像素矩阵的所述光电流模式提供防晕能力，并且允许在多个像素之间共享某些像素电路元件。

7. 发明申请

WO2006010615A1 LAYOUTS FOR THE MONOLITHIC INTEGRATION OF CMOS AND DEPOSITED PHOTONIC ACTIVE LAYERS 审中-公开
标题翻译：用于CMOS和沉积的光子活性层的单片集成的方法
公开(公告)号：WO2006010615A1
公开(公告)日：2006-02-02
申请号：PCT/EP2005/008182
申请日：2005-07-28
申请人： QUANTUM SEMICONDUCTOR LLC , AUGUSTO, Carlos, J.R.P.
发明人： AUGUSTO, Carlos, J.R.P.
IPC分类号： H01L27/146
CPC分类号： H01L27/146 , H01L27/14603 , H01L27/14609 , H01L27/1463 , H01L27/14643 , H01L27/156
摘要： Several detailed layout designs are disclosed, for the monolithic integration of avalanche devices in large arrays, that can be operated as Avalanche Photo-Diodes (APDs) or Avalanche Light Emitting Diodes (ALEDs) depending only on the applied bias conditions, which can be software-controlled from peripheral circuitry. If the deposited films have direct bandgaps, then the devices can emit light even in the absence of avalanche operation. In particular, the layouts according to the invention comprise a sensor/emitter matrix achieved through the replication of basic Pixel/Lixel cells.
摘要翻译：公开了几种详细的布局设计，用于大型阵列中的雪崩器件的单片集成，其可以仅依赖于施加的偏置条件而被操作为雪崩光二极管（APD）或雪崩发光二极管（ALED），其可以是软件由外设电路控制。如果沉积的膜具有直接的带隙，则即使在没有雪崩操作的情况下，器件也可以发光。特别地，根据本发明的布局包括通过复制基本像素/透镜单元实现的传感器/发射器矩阵。

8. 发明申请

WO2017059146A1 ELECTRICAL DEVICES MAKING USE OF COUNTERDOPED JUNCTIONS 审中-公开
标题翻译：电气设备使用计数器的连接
公开(公告)号：WO2017059146A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/054560
申请日：2016-09-29
申请人： QUANTUM SEMICONDUCTOR LLC
发明人： AUGUSTO, Carlos, Jorge
IPC分类号： H01L21/04 , H01L29/15 , H01L21/265 , H01L29/737 , H01L31/00
CPC分类号： H01L27/14612 , H01L27/14601 , H01L27/1461 , H01L27/14681 , H01L29/0653 , H01L29/0821 , H01L29/1004 , H01L29/155 , H01L29/7371 , H01L31/00
摘要： An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species. The device also includes a first counterdoped component selected from a group consisting of the first semiconductor and the second semiconductor. The first counterdoped component is counterdoped with one or more counterdopant species that have a polarity opposite to the polarity of the primary dopant included in the first counterdoped component. Additionally, a level of the n-type primary dopant, p-type primary dopant, and the one or more counterdopant is selected to the counterdoped heterojunction provides amplification by a phonon assisted mechanism and the amplification has an onset voltage less than 1 V.
摘要翻译：电气装置包括选自由pn结或p-i-n结组成的组的反掺杂异质结。反向接合点包括掺杂有一个或多个n型初级掺杂物种的第一半导体和掺杂有一种或多种p型主掺杂物种的第二半导体。该器件还包括从由第一半导体和第二半导体组成的组中选择的第一反向掺杂元件。第一反向组分与一个或多个反掺杂物质相反，其具有与包含在第一反掺杂组分中的主要掺杂物的极性相反的极性。此外，选择n型初级掺杂剂，p型初级掺杂剂和一种或多种反掺杂剂的水平用于反向掺杂的异质结，通过声子辅助机制提供扩增，并且扩增具有小于1V的起始电压。

9. 发明申请

WO2009103048A1 DUAL PHOTO-DIODE CMOS PIXELS 审中-公开
标题翻译：双光电二极管CMOS像素
公开(公告)号：WO2009103048A1
公开(公告)日：2009-08-20
申请号：PCT/US2009/034211
申请日：2009-02-16
申请人： QUANTUM SEMICONDUCTOR LLC
发明人： AUGUSTO, Carlos
IPC分类号： H01L27/146
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L27/14647
摘要： The present invention provides a method of forming CMOS pixels, with the light-sensing region comprising vertically aligned dual photo-diodes, in which the bottom photo-diode is formed either by a well-to-substrate junction, or by a deep-well-to-substrate junction, wherein said well and deep-well are independently biased from surrounding wells and deep-wells of the same polarity. Said independently biased well is a common region to the top and bottom photo-diodes and overlaps the source/drain region of a MOSFET formed on a well with the opposite polarity, that of the substrate. The photo-diodes can be electrically connected in parallel, or the top photo- diode can be biased separately from the bottom photo-diode, said bias can be such that avalanche mode operation is possible, including the single-photon detection (Geiger) mode.
摘要翻译：本发明提供了一种形成CMOS像素的方法，其中光感测区域包括垂直对准的双光电二极管，其中底部光电二极管由阱到衬底结或由深阱形成其中所述阱和深阱独立地偏置于相同极性的周围阱和深阱。所述独立偏置井是顶部和底部光电二极管的公共区域，并且与形成在具有相反极性的衬底的阱的MOSFET的源极/漏极区域重叠。光电二极管可以并联电连接，或者顶部光电二极管可以与底部光电二极管分开偏置，所述偏置可以使得雪崩模式操作是可能的，包括单光子检测（盖革）模式。

10. 发明申请

WO2009030980A2 LIGHT-TUNNELS FOR PIXEL ARRAYS 审中-公开
标题翻译：像素阵列的轻型隧道
公开(公告)号：WO2009030980A2
公开(公告)日：2009-03-12
申请号：PCT/IB2007004682
申请日：2007-09-06
申请人： QUANTUM SEMICONDUCTOR LLC , AUGUSTO CARLOS J R P
发明人： AUGUSTO CARLOS J R P
CPC分类号： G02B6/1225 , G02B6/08 , G02B6/12 , G02B6/4249 , G02B6/4298 , G02B6/43 , G02B2006/12166 , G02B2006/12176 , H01L27/14621 , H01L27/14629 , H01L27/14636 , H01L27/14685 , H01L31/0232
摘要： Light guiding structures are provided to improve the light coupling between photonic active devices and the top of a metallization layer stack interconnecting these photonic active devices. Each light guiding structure comprises a hole extending between the near surface of the photonic active devices and the top surface of the metallization layer stack, said hole being filled with dielectrics or a combination of dielectrics and metals. Such a light guiding structure removes from the optical path of light rays, the interfaces between the metallization layers, thereby confining light laterally and enabling interconnects with increased thickness and more levels of metal. This results in the suppression of multiple reflections and optical crosstalk. The light guiding structures can have cross-section diagonals with sub-wavelength dimensions can be fabricated after all CMOS process steps, thus having minimal interference and maximal compatibility with CMOS processing.
摘要翻译：提供导光结构以改善光子有源器件与互连这些光子有源器件的金属化层堆叠的顶部之间的光耦合。每个导光结构包括在光子有源器件的近表面和金属化层堆叠的顶表面之间延伸的孔，所述孔填充有电介质或电介质和金属的组合。这种导光结构从光线的光路，金属化层之间的界面移除，从而横向限制光，并且实现具有增加的厚度和更多的金属水平的互连。这导致抑制多重反射和光学串扰。导光结构可以具有横截面对角线，亚波长尺寸可以在所有CMOS工艺步骤之后制造，因此具有最小的干扰和与CMOS处理的最大兼容性。

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