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1. 发明申请

WO99063598A1 SEMICONDUCTOR CURRENT-SWITCHING DEVICE HAVING OPERATIONAL ENHANCER AND METHOD THEREFOR 审中-公开
标题翻译：具有操作增强器的半导体电流切换装置及其方法
公开(公告)号：WO99063598A1
公开(公告)日：1999-12-09
申请号：PCT/US1999/012481
申请日：1999-06-01
IPC分类号： G11C11/41 , G11C11/39 , H01L21/8244 , H01L27/06 , H01L27/11 , H01L29/417 , H01L29/423 , H01L29/74 , H01L29/87
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A novel small-area NDR-based circuit can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR-based circuit uses a thin vertical PNPN structure (10) with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new cell is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption.
摘要翻译：一种新型的小面积NDR电路可用于实现各种半导体电路，包括高密度SRAM单元和功率晶闸管结构。在一个示例实施例中，基于NDR的电路使用具有电容耦合的门辅助关断和导通机制的薄垂直PNPN结构（10）。基于这个新单元的SRAM在单元面积，待机电流，架构，速度和制造过程中与相同容量的DRAM相当。在一个实施例中，基于NDR的SRAM单元仅由两个元件组成，可以在高速和低电压下工作，具有良好的噪声余量，并且在与主流CMOS的制造过程中兼容。该电池显着降低待机功耗。

2. 发明申请

WO2016049608A1 POWER REDUCTION IN THYRISTOR RANDOM ACCESS MEMORY 审中-公开
标题翻译：电路随机访问存储器中的功率减少
公开(公告)号：WO2016049608A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052507
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie
IPC分类号： G11C7/00
CPC分类号： H01L27/1027 , G06F11/1048 , G11C11/39 , G11C11/4026 , G11C11/406 , G11C11/4067 , G11C11/408 , G11C11/4094 , H01L21/76 , H01L21/76224 , H01L27/1023 , H01L29/66121 , H01L29/87
摘要： A volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays.
摘要翻译：公开了使用垂直晶闸管的易失性存储器阵列以及降低这种阵列中的功率消耗的方法。

3. 发明申请

WO2016049601A1 THYRISTOR VOLATILE RANDOM ACCESS MEMORY AND METHODS OF MANUFACTURE 审中-公开
标题翻译： THYRISENT VOLATILE RANDOM ACCESS MEMORY AND METHODS OF MANUFACTURE
公开(公告)号：WO2016049601A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052499
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie
IPC分类号： G11C11/00 , H01L21/76 , H01L27/00
CPC分类号： H01L27/1027 , G06F11/1048 , G11C11/39 , G11C11/4026 , G11C11/406 , G11C11/4067 , G11C11/408 , G11C11/4094 , H01L21/76 , H01L21/76224 , H01L27/1023 , H01L29/66121 , H01L29/87
摘要： A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.
摘要翻译：公开了使用垂直晶闸管的易失性存储器阵列以及制造阵列的方法。

4. 发明申请

WO2012118614A3 GATED BIPOLAR JUNCTION TRANSISTORS, MEMORY ARRAYS, AND METHODS OF FORMING GATED BIPOLAR JUNCTION TRANSISTORS 审中-公开
标题翻译：栅极双极晶体管，存储器阵列和形成双极晶体管晶体管的方法
公开(公告)号：WO2012118614A3
公开(公告)日：2012-11-22
申请号：PCT/US2012025115
申请日：2012-02-14
申请人： MICRON TECHNOLOGY INC , GUPTA RAJESH N , NEMATI FARID , ROBINS SCOTT T
发明人： GUPTA RAJESH N , NEMATI FARID , ROBINS SCOTT T
IPC分类号： H01L29/73 , H01L27/082 , H01L27/102
CPC分类号： H01L27/1026 , H01L21/02381 , H01L21/02529 , H01L21/8229 , H01L27/1023 , H01L27/1024 , H01L27/10802 , H01L29/1608 , H01L29/73 , H01L29/732 , H01L29/735 , H01L29/7391 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
摘要翻译：一些实施例包括门极双极结型晶体管。晶体管可以包括在集电极区域和发射极区域之间的基极区域; 其中B-C结位于基极区和集电极区的界面处，并且B-E结位于基极区和发射极区的界面处。晶体管可以包括在一个或多个基极，发射极和集电极区内具有至少1.2eV的带隙的材料。栅极晶体管可以包括沿着基极区域的栅极并且通过电介质材料与基极区域间隔开，栅极不与B-C结或B-E结重叠。一些实施例包括包含门极双极结型晶体管的存储器阵列。一些实施例包括形成门控双极结型晶体管的方法。

5. 发明申请

WO2006066890A1 BIPOLAR READING TECHNIQUE FOR A MEMORY CELL HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR 审中-公开
标题翻译：具有电浮动体晶体管的记忆体的双极读取技术
公开(公告)号：WO2006066890A1
公开(公告)日：2006-06-29
申请号：PCT/EP2005/013755
申请日：2005-12-21
申请人： INNOVATIVE SILICON S.A. , OKHONIN, Serguei , NAGOGA, Mikhail
发明人： OKHONIN, Serguei , NAGOGA, Mikhail
IPC分类号： H01L29/78 , H01L27/108 , G11C11/404
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016 , H01L27/1023 , H01L27/108 , H01L29/78 , H01L29/7841
摘要： A technique of sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, the present inventions are directed to a memory cell, having an electrically floating body transistor, and/or a technique of reading the data state in such a memory cell. In this regard, the present inventions employ the intrinsic bipolar transistor current to read and/or determine the data state of the electrically floating body memory cell (for example, whether the electrically floating body memory cell is programmed in a State "0" and State "'I"). During the read operation, the data state is determined primarily by or sensed substantially using the bipolar current responsive to the read control signals and significantly less by the interface channel current component, which is negligible relatively to the bipolar component. The bipolar transistor current may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor. As such, the programming window obtainable with the bipolar reading technique may be considerably higher (for example, up two orders of magnitude higher) than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component.
摘要翻译：一种对存储单元阵列（例如具有由电浮体晶体管组成的多个存储单元的存储单元阵列）的存储单元的数据状态进行采样，检测，读取和/或确定的技术。在一个实施例中，本发明涉及具有电浮体晶体管的存储单元，和/或在这种存储单元中读取数据状态的技术。在这方面，本发明使用本征双极晶体管电流来读取和/或确定电浮动体存储单元的数据状态（例如，电浮动体存储单元是否被编程在状态“0”和状态 “'一世”）。在读取操作期间，数据状态主要由或基本上使用响应于读取的控制信号的双极性电流确定，并且显着地小于相对于双极组件可忽略的界面通道电流分量。由于本征双极晶体管的高增益，双极晶体管电流可能对浮体电位非常敏感。因此，采用双极读取技术可获得的编程窗口可以比采用常规读取技术（主要基于接口通道电流分量的编程窗口）高得多（例如，高两个数量级）。

6. 发明申请

WO2017139286A1 IMPROVED VERTICAL THYRISTOR MEMORY WITH MINORITY CARRIER LIFETIME REDUCTION 审中-公开
标题翻译：利用少数载波寿命降低改善垂直晶闸管存储器
公开(公告)号：WO2017139286A1
公开(公告)日：2017-08-17
申请号：PCT/US2017/016865
申请日：2017-02-07
申请人： KILOPASS TECHNOLOGY, INC.
发明人： CHENG, Charlie , AXELRAD, Valery , LUAN, Harry
IPC分类号： H01L27/08 , H01L27/102
CPC分类号： H01L27/1027 , G11C11/39 , H01L21/02271 , H01L21/221 , H01L21/26513 , H01L21/28518 , H01L21/28525 , H01L21/28562 , H01L21/28568 , H01L21/32053 , H01L21/8229 , H01L23/53209 , H01L23/53242 , H01L27/0817 , H01L27/1023 , H01L27/10802 , H01L28/00 , H01L29/0642 , H01L29/0649 , H01L29/0839 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/456 , H01L29/66363 , H01L29/74 , H01L29/87
摘要： Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.
摘要翻译：这里描述了用于减少存储器阵列中的少数载流子的装置和方法。少数载流子在ON单元和OFF单元之间扩散，在写操作期间造成干扰并且减少单元的保持寿命。描述了具有绝缘沟槽的垂直晶闸管存储器阵列的少数载流子寿命终止器（MCLK）区域架构。这些MCLK区域鼓励少数载流子的重组。特别地，描述了由沿着晶闸管阵列的阴极线嵌入的导体形成的MCLK区域以及掺杂剂MCLK区域，以及用于制造具有MCLK区域的晶闸管存储器单元的方法。

7. 发明申请

WO2016049606A1 METHODS OF RETAINING AND REFRESHING DATA IN A THYRISTOR RANDOM ACCESS MEMORY 审中-公开
标题翻译：保持和刷新数据在方法随机存取存储器中的方法
公开(公告)号：WO2016049606A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052505
申请日：2015-09-25
申请人： KILOPASS TECHNOLOGY, INC.
发明人： LUAN, Harry , BATEMAN, Bruce , AXELRAD, Valery , CHENG, Charlie
IPC分类号： G11C11/34
CPC分类号： H01L27/1027 , G06F11/1048 , G11C11/39 , G11C11/4026 , G11C11/406 , G11C11/4067 , G11C11/408 , G11C11/4094 , H01L21/76 , H01L21/76224 , H01L27/1023 , H01L29/66121 , H01L29/87
摘要： A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.
摘要翻译：公开了使用垂直晶闸管的易失性存储器阵列以及操作阵列以读取，写入，保留和刷新存储在其中的数据的方法。

8. 发明申请

WO2014092224A1 비대칭 2-단자 바이리스터 소자와 그 제작 방법 审中-公开
标题翻译：非对称双端子元件及其制造方法
公开(公告)号：WO2014092224A1
公开(公告)日：2014-06-19
申请号：PCT/KR2012/010972
申请日：2012-12-15
申请人： 한국과학기술원
发明人： 최양규 , 문동일 , 최성진
IPC分类号： H01L27/105 , H01L27/108 , H01L21/8242
CPC分类号： H01L27/1023 , H01L27/10802 , H01L29/8615
摘要： 본 발명의 실시 예는 비대칭 2-단자 바이리스터 소자와 그 제작 방법에 관한 것이다. 실시 예에 따른 비대칭 2-단자 바이리스터 소자는, 기판; 상기 기판 상에 형성된 제1반도체 층; 상기 제1반도체 층 상에 형성된 제2반도체 층; 상기 제2반도체 층 상에 형성된 제3반도체 층; 상기 제1반도체 층과 전기적으로 연결된 제1전도층; 및 상기 제3반도체 층과 전기적으로 연결된 제2전도층;을 포함하고, 상기 제2반도체 층은 제1불순물 영역과 제2불순물 영역을 갖고, 상기 제1불순물 영역의 농도는 상기 제2불순물 영역의 농도보다 크다.
摘要翻译：本发明的一个实施例涉及一种不对称的2端子半导体元件及其制造方法。根据实施例的非对称2端子半导体元件包括：基板; 形成在所述基板上的第一半导体层; 形成在所述第一半导体层上的第二半导体层; 形成在所述第二半导体层上的第三半导体层; 电连接到第一半导体层的第一导电层; 和与第三半导体层电连接的第二导电层，其中第二半导体层具有第一杂质区和第二杂质区，第一杂质区的浓度大于第二杂质区的浓度。

9. 发明申请

WO2012118614A2 GATED BIPOLAR JUNCTION TRANSISTORS, MEMORY ARRAYS, AND METHODS OF FORMING GATED BIPOLAR JUNCTION TRANSISTORS 审中-公开
标题翻译：门控双极结型晶体管，存储阵列和形成门控双极结型晶体管的方法
公开(公告)号：WO2012118614A2
公开(公告)日：2012-09-07
申请号：PCT/US2012/025115
申请日：2012-02-14
申请人： MICRON TECHNOLOGY, INC. , GUPTA, Rajesh, N. , NEMATI, Farid , ROBINS, Scott, T.
发明人： GUPTA, Rajesh, N. , NEMATI, Farid , ROBINS, Scott, T.
IPC分类号： H01L29/73 , H01L27/102 , H01L27/082
CPC分类号： H01L27/1026 , H01L21/02381 , H01L21/02529 , H01L21/8229 , H01L27/1023 , H01L27/1024 , H01L27/10802 , H01L29/1608 , H01L29/73 , H01L29/732 , H01L29/735 , H01L29/7391 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
摘要翻译：一些实施例包括门控双极结型晶体管。晶体管可以包括集电极区和发射极区之间的基极区; 其中B-C结处于基极区和集电极区的界面处，并且B-E结处于基极区和发射极区的界面处。晶体管可以包括在一个或多个基极，发射极和集电极区域内具有至少1.2eV的带隙的材料。栅控晶体管可以包括沿着基极区域的栅极并且通过介电材料与基极区域隔开，其中栅极不与B-C结或B-E结交叠。一些实施例包括含有门控双极结型晶体管的存储器阵列。一些实施例包括形成门控双极结晶体管的方法。

10. 发明申请

WO2004036587A1 MEMORY CELL FOR A DYNAMIC STORING DEVICE 审中-公开
标题翻译：动态存储设备的存储单元
公开(公告)号：WO2004036587A1
公开(公告)日：2004-04-29
申请号：PCT/RU2002/000458
申请日：2002-10-21
IPC分类号： G11C11/40
CPC分类号： G11C11/405 , H01L27/0722 , H01L27/1023
摘要： The invention relates to nanoelectronics. The introduction of a bipolar transistor and a non-linear resistor into a memory cell increases the reliability and speed thereof. The inventive memory cell in embodied in the form of a functional-integrated element in which the collector area of the bipolar transistor is simultaneously used as a gate area of a MOSFET transistor. The drain region (D) of said MOSFET transistor forms the region (B) of the bipolar transistor, a resistor being formed by the quasi-neutral part of the active region of the base (p) of the bipolar transistor The functional integration of the MOSFET and the bipolar transistors in a single structure constructs the memory cell according the layout and the production technology of the similar one-transistor memory cells for core memory devices with a random generation of information.
摘要翻译：本发明涉及纳米电子学。将双极晶体管和非线性电阻器引入存储单元增加其可靠性和速度。本发明的存储单元以功能集成元件的形式实现，其中双极晶体管的集电极区域同时用作MOSFET晶体管的栅极区域。所述MOSFET晶体管的漏极区域（D）形成双极晶体管的区域（B），由双极晶体管的基极（p）的有源区的准中性部分形成的电阻器。 MOSFET和单个结构中的双极晶体管根据具有随机生成信息的核心存储器件的类似的单晶体管存储器单元的布局和生产技术构建存储器单元。

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