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1. 发明申请

WO2004084299A3 SHALLOW TRENCH ISOLATION IN PROCESSES WITH STRAINED SILICON 审中-公开
公开(公告)号：WO2004084299A3
公开(公告)日：2004-09-30
申请号：PCT/US2004/007464
申请日：2004-03-11
申请人： ADVANCED MICRO DEVICES, INC. , WANG, Haihong , NGO, Minh, Van , XIANG, Qi , BESSER, Paul, R. , PATON, Eric, N. , LIN, Ming-Ren
发明人： WANG, Haihong , NGO, Minh, Van , XIANG, Qi , BESSER, Paul, R. , PATON, Eric, N. , LIN, Ming-Ren
IPC分类号： H01L21/762
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

2. 发明申请

WO2004066368A2 SHALLOW TRENCH ISOLATION PROCESS FOR STRAINED SILICON PROCESSES 审中-公开
标题翻译：用于应变硅工艺的浅层分离工艺
公开(公告)号：WO2004066368A2
公开(公告)日：2004-08-05
申请号：PCT/US2004/000982
申请日：2004-01-13
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh-Van , XIANG, Qi , BESSER, Paul, R. , PATON, Eric, N. , LIN, Ming-Ren
发明人： NGO, Minh-Van , XIANG, Qi , BESSER, Paul, R. , PATON, Eric, N. , LIN, Ming-Ren
IPC分类号： H01L
CPC分类号： H01L21/76224
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can form the liner.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。低温过程可以是LPCVD。退火步骤可以形成衬套。

3. 发明申请

WO2003036701A1 LOW-TEMPERATURE POST-DOPANT ACTIVATION PROCESS 审中-公开
标题翻译：低温后激活过程
公开(公告)号：WO2003036701A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/032555
申请日：2002-10-11
申请人： ADVANCED MICRO DEVICES, INC. , YU, Bin , OGLE, Robert, B. , PATON, Eric, N. , TABERY, Cyrus, E. , XIANG, Qi
发明人： YU, Bin , OGLE, Robert, B. , PATON, Eric, N. , TABERY, Cyrus, E. , XIANG, Qi
IPC分类号： H01L21/268
CPC分类号： H01L29/665 , H01L21/268
摘要： A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode (24) over a substrate (10) and a gate oxide (16) between the gate electrode (24) and the substrate (10); forming source/drain extensions (30, 32) in the substrate (10); forming first and second sidewall spacers (36, 38); implanting dopants (44) within the substrate (10) to form source/drain regions (40, 42) in the substrate (10) adjacent to the sidewalls spacers (36, 38); laser thermal annealing to activate the source/drain regions (40, 42); depositing a layer of nickel (46) over the source/drain regions (40, 42); and annealing to form a nickel silicide layer (46) disposed on the source/drain regions (40, 42). The source/drain extensions (30, 32) and sidewall spacers (36, 38) are adjacent to the gate electrode (24). The source/drain extensions (30, 32) can have a depth of about 5 to 30 nanometers, and the source/drain regions (40, 42) can have a depth of about 40 to 100 nanometers. The annealing is at temperatures from about 350 to 500 °C.
摘要翻译：一种制造MOSFET半导体器件的方法包括在栅电极（24）和衬底（10）之间的衬底（10）和栅氧化层（16）上形成栅电极（24）。在所述衬底（10）中形成源极/漏极延伸部（30,32）; 形成第一和第二侧壁间隔件（36,38）; 在所述衬底（10）内注入掺杂剂（44）以在所述衬底（10）中邻近所述侧壁间隔物（36,38）形成源/漏区（40,42）; 激光热退火以激活源/漏区（40,42）; 在源/漏区（40,42）上沉积一层镍（46）; 和退火以形成设置在源/漏区（40,42）上的硅化镍层（46）。源极/漏极延伸部（30,32）和侧壁间隔物（36,38）与栅电极（24）相邻。源极/漏极扩展部（30,32）可以具有约5至30纳米的深度，并且源极/漏极区域（40,42）可以具有约40至100纳米的深度。退火温度在约350-500℃

4. 发明申请

WO2003021662A1 IMPROVED HIGH K-DIELECTRICS USING NICKEL SILICIDE 审中-公开
标题翻译：改善使用镍硅胶的高K电介质
公开(公告)号：WO2003021662A1
公开(公告)日：2003-03-13
申请号：PCT/US2002/010478
申请日：2002-04-05
申请人： ADVANCED MICRO DEVICES, INC.
发明人： XIANG, Qi , BESSER, Paul, R. , BUYNOSKI, Matthew, S. , FOSTER, John, Clayton , KING, Paul, L. , PATON, Eric, N.
IPC分类号： H01L21/336
CPC分类号： H01L29/4933 , H01L21/28167 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/665
摘要： A method for preventing the thermal decomposition of a high-K deilectric layer (12) of a gate electrode (14) during the formation of a metal silicide (22, 24) on the gate electrode (14) by using nickel as the metal component of the silicide (22, 24).
摘要翻译：一种用于在通过使用镍作为金属成分在栅电极（14）上形成金属硅化物（22,24）期间防止栅电极（14）的高K电介质层（12）的热分解的方法的硅化物（22,24）。

5. 发明申请

WO2002065523A1 GATE ELECTRODE SILICIDATION LAYER 审中-公开
标题翻译：门电极硅化层
公开(公告)号：WO2002065523A1
公开(公告)日：2002-08-22
申请号：PCT/US2001/043807
申请日：2001-11-13
申请人： ADVANCED MICRO DEVICES, INC.
发明人： PATON, Eric, N. , BESSER, Paul, R. , BUYNOSKI, Matthew, S. , XIANG, Qi , KING, Paul, L. , FOSTER, John, Clayton
IPC分类号： H01L21/28
CPC分类号： H01L21/28061 , H01L21/28052 , H01L29/4941
摘要： Controlled silicidation of a gate electrode layer is implemented using a silicide stop layer (28). Initially, a gate dielectric layer (19) is formed over a semiconductor substrate (21) and a first silicon layer (26) is then formed on the gate dielectric layer (19). A silicide stop layer (28) is then deposited over the first silicon layer (26) amd a second silicon layer (30) is deposited over the silicide stop layer (28). A metal or an alloy layer (34) is then deposited over the second silicon layer (30) and heating is conducted to react the metal or metal ally (34) with underlying silicon (28) to form a metal silicide layer (36, 38), silicidation ceasing upon reaching the silicide stop layer (28).
摘要翻译：使用硅化物阻挡层（28）实现栅极电极层的受控硅化。首先，在半导体衬底（21）上形成栅介质层（19），然后在栅介电层（19）上形成第一硅层（26）。然后在硅化物停止层（28）上沉积第二硅层（30）之后，在第一硅层（26）上沉积硅化物阻挡层（28）。然后将金属或合金层（34）沉积在第二硅层（30）上，并进行加热以使金属或金属烯（34）与下面的硅（28）反应以形成金属硅化物层（36,38 ），硅化物在到达硅化物停止层（28）时停止。

6. 发明申请

WO2004038807A1 MOSFETS INCORPORATING NICKEL GERMANOSILICIDED GATE AND METHODS OF THEIR FORMATION 审中-公开
标题翻译：锰合金镍合金门锗及其形成方法
公开(公告)号：WO2004038807A1
公开(公告)日：2004-05-06
申请号：PCT/US2003/028680
申请日：2003-09-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： PATON, Eric, N. , XIANG, Qi , BESSER, Paul, R. , LIN, Ming-Ren , NGO, Minh, Van , WANG, Haihong
IPC分类号： H01L29/78
CPC分类号： H01L29/4933 , H01L21/28052 , H01L29/1054 , H01L29/4908 , H01L29/66477 , H01L29/665 , H01L29/66795 , H01L2029/7858
摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide (62, 64) that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.
摘要翻译： MOSFET栅极或MOSFET源极或漏极区域包括硅锗或多晶硅锗。进行镍的硅化以形成优选包含硅化镍的一硅化物相的锗硅酸镍（62,64）。在硅化物中包含锗提供了可以形成单硅化物相的更宽的温度范围，同时基本上保持了一氧化硅镍表现出的优异的薄层电阻。因此，在后续处理中，锗硅酸镍能够耐受比一次硅化镍更高的温度，同时提供了与一氧化硅一样的大致相同的薄层电阻和其他有益的性能。

7. 发明申请

WO2004001826A1 METHOD USING SILICIDE CONTACTS FOR SEMICONDUCTOR PROCESSING 审中-公开
标题翻译：使用硅化物接触进行半导体加工的方法
公开(公告)号：WO2004001826A1
公开(公告)日：2003-12-31
申请号：PCT/US2003/017599
申请日：2003-06-04
申请人： ADVANCED MICRO DEVICES, INC.
发明人： BESSER, Paul, R. , CHAN, Simon, S. , BROWN, David, E. , PATON, Eric, N.
IPC分类号： H01L21/285
CPC分类号： H01L21/28518
摘要： A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal (such as nickel) that is capable of forming one or more metal silicides and a material (such as Ge, Ti, Re, Ta, N, V, Jr, Cr, Zr if the metal is nickel) that is soluble in a first metal silicide (such as NiSi) but not soluble in a second metal silicide (such as NiSi 2 ), or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide. The contacts may be part of a semiconductor device including a substrate, active region containing silicon, and silicide contacts disposed over the active region and capable of electrically coupling the active region to other regions such as metallization lines.
摘要翻译：用于形成硅化物接触的方法包括在诸如源极，漏极和栅极区域的含硅有源器件区域上形成层。该层含有能够形成一种或多种金属硅化物的金属（例如镍）和材料（例如，如果金属为镍，则为Ge，Ti，Re，Ta，N，V，Jr，Cr，Zr）可溶于第一金属硅化物（例如NiSi），但不溶于第二金属硅化物（例如NiSi 2），或者比在第二金属硅化物中更溶于第一金属硅化物。该层可以通过诸如物理气相沉积，化学气相沉积，蒸发，激光烧蚀或其它沉积方法之类的气相沉积方法形成。形成硅化物接触的方法包括形成金属层，然后用如上所述的材料注入金属层和/或下层硅层。在形成金属层之前，材料可以被植入到硅层中。形成的触点包括第一金属硅化物和比在第二金属硅化物中更溶于第一金属硅化物的材料。触点可以是半导体器件的一部分，其包括衬底，含硅的有源区和设置在有源区上的硅化物触点，并且能够将有源区电耦合到诸如金属化线的其它区域。

8. 发明申请

WO2002065524A1 SILICIDE STOP LAYER IN A DAMASCENE GATE SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：大气阻挡层半导体结构中的硅化物停留层
公开(公告)号：WO2002065524A1
公开(公告)日：2002-08-22
申请号：PCT/US2001/043896
申请日：2001-11-13
申请人： ADVANCED MICRO DEVICES, INC.
发明人： PATON, Eric, N. , BESSER, Paul, R. , BUYNOSKI, Matthew, S. , XIANG, Qi , KING, Paul, L. , FOSTER, John, Clayton
IPC分类号： H01L21/28
CPC分类号： H01L29/66583 , H01L21/28052 , H01L29/4941
摘要： A damascene gate semiconductor structure that is formed utilizing a silicide stop layer (34). Initially, a gate opening (28) is provided in an insulating layer (26) on a substrate (24). A first dielectric layer (30) is deposited in the gate opening (28) over the substrate (24). A silicide stop layer (34) is then deposited in the gate opening (28) over the first silicon layer (32). A second silicon layer (36) is then deposited in the gate opening (28) over the silicide stop layer (34). A metal or alloy layer (38) is then deposited over the insulating layer (26) and the second silicon layer (38). The damascene semiconductor structure is then temperature treated to react the metal or alloy layer (38) with the second silicon layer (36) to form a silicide layer (40). Any unreacted metal or alloy is then removed from the metal or alloy layer (38).
摘要翻译：利用硅化物停止层（34）形成的镶嵌栅极半导体结构。首先，在基板（24）上的绝缘层（26）中设置栅极开口（28）。第一电介质层（30）沉积在衬底（24）上的栅极开口（28）中。然后将硅化物阻挡层（34）沉积在第一硅层（32）上的栅极开口（28）中。然后在栅极开口（28）上沉积硅化物阻挡层（34）上的第二硅层（36）。然后在绝缘层（26）和第二硅层（38）上沉积金属或合金层（38）。然后对镶嵌半导体结构进行温度处理以使金属或合金层（38）与第二硅层（36）反应以形成硅化物层（40）。然后从金属或合金层（38）中除去任何未反应的金属或合金。

9. 发明申请

WO2004061920A3 METHOD OF FORMING A THICK STRAINED SILICON LAYER AND SEMICONDUCTOR STRUCTURES INCORPORATING A THICK STRAINED SILICON LAYER 审中-公开
公开(公告)号：WO2004061920A3
公开(公告)日：2004-07-22
申请号：PCT/US2003/034673
申请日：2003-10-30
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WANG, Haihong , BESSER, Paul, R. , GOO, Jung-Suk , NGO, Minh, Van , PATON, Eric, N. , XIANG, Qi
IPC分类号： H01L21/20
摘要： A strained silicon layer (50) s grown on a layer of silicon germanium (40) and a layer of silicon germanium (52) is grown on the strained silicon (50) in a single continuous in situ deposition process with the strained silicon (50). Shallow trench isolations (48) are formed in the lower layer of silicon germanium (40) prior to formation of the strained silicon layer (50). The two silicon germanium layers (40, 52) effectively provide dual substrates at both surfaces of the strained silicon layer (50) that serve to maintain the tensile strain of the strained silicon layer (50) and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon (50) that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers (40, 52). The formation of shallow trench isolations (48) prior to formation of the strained silicon layer (50) avoids subjecting the strained silicon (50) layer to extreme thermal stresses and further reduces the formation of misfit dislocations.

10. 发明申请

WO2004040622A2 NICKEL SILICIDE WITH REDUCED INTERFACE ROUGHNESS 审中-公开
标题翻译：镍化硅具有降低的界面粗糙度
公开(公告)号：WO2004040622A2
公开(公告)日：2004-05-13
申请号：PCT/US2003/014982
申请日：2003-05-13
申请人： ADVANCED MICRO DEVICES, INC.
发明人： PATON, Eric, N. , BESSER, Paul, R. , CHAN, Simon, S. , HAUSE, Fred, N.
IPC分类号： H01L21/00
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28052 , H01L29/665 , H01L29/6659
摘要： Nickel silicide (63, 64) formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer (61, 62) between the underlying silicon (22, 26) and nickel silicide layers (63, 64). Embodiments include ion implanting nitrogen (31, 32) into the substrate (20) and gate electrode (22), depositing a thin layer of titanium or tantalum (40), depositing a layer of nickel (50), and then heating to form a diffusion modulating layer (61, 62) containing nitrogen at the interface between the underlying silicon (22, 26) and nickel silicide layers (63, 64).
摘要翻译：通过在下面的硅（22,26）和硅化镍层（63,64）之间形成扩散调节层（61,62）来实现具有显着降低的界面粗糙度的硅化镍（63,64） 64）。实施例包括将氮（31,32）离子注入到衬底（20）和栅电极（22）中，沉积钛或钽薄层（40），沉积镍层（50），然后加热以形成在下面的硅（22,26）和硅化镍层（63,64）之间的界面处含有氮的扩散调节层（61,62）。

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