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1. 发明申请

WO2012125580A3 NON-VOLATILE ANTI-FUSE MEMORY CELL 审中-公开
公开(公告)号：WO2012125580A3
公开(公告)日：2012-09-20
申请号：PCT/US2012/028809
申请日：2012-03-12
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , MITCHELL, Allan, T. , ESKEW, Mark, A. , JARREAU, Keith
发明人： MITCHELL, Allan, T. , ESKEW, Mark, A. , JARREAU, Keith
IPC分类号： H01L27/115 , H01L21/8247
摘要： A non-volatile anti-fuse memory cell includes a programmable n-channel diode-connectable transistor (300). The polysilicon gate (308) of the transistor has two portions. One portion is doped more highly than the other portion. The transistor also has a source (312) with two portions where one portion of the source is doped more highly than the other portion. The portion of the gate (308) that is physically closer to the source is more lightly doped than the other portion of the gate. The portion of the source (312) that is physically closer to the lightly doped portion of the gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the polysilicone gate that is heavily doped. A p-channel transistor is also disclosed.

2. 发明申请

WO2012125580A2 NON-VOLATILE ANTI-FUSE MEMORY CELL 审中-公开
标题翻译：非易失性的反熔丝内存单元
公开(公告)号：WO2012125580A2
公开(公告)日：2012-09-20
申请号：PCT/US2012028809
申请日：2012-03-12
申请人： TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , MITCHELL ALLAN T , ESKEW MARK A , JARREAU KEITH
发明人： MITCHELL ALLAN T , ESKEW MARK A , JARREAU KEITH
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11206 , G11C17/16 , H01L27/11226 , H01L29/4983 , H01L29/861
摘要： A non-volatile anti-fuse memory cell includes a programmable n-channel diode-connectable transistor (300). The polysilicon gate (308) of the transistor has two portions. One portion is doped more highly than the other portion. The transistor also has a source (312) with two portions where one portion of the source is doped more highly than the other portion. The portion of the gate (308) that is physically closer to the source is more lightly doped than the other portion of the gate. The portion of the source (312) that is physically closer to the lightly doped portion of the gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the polysilicone gate that is heavily doped. A p-channel transistor is also disclosed.
摘要翻译：非易失性反熔丝存储单元包括可编程的n沟道二极管可连接晶体管（300）。晶体管的多晶硅栅极（308）具有两个部分。一部分比另一部分掺杂得更高。晶体管还具有源极（312），其具有两个部分，其中源极的一部分比另一部分掺杂得更高。物理上更接近源极的栅极（308）的部分比栅极的另一部分更轻掺杂。物理上更靠近栅极的轻掺杂部分的源极（312）的部分相对于源极的另一部分轻微掺杂。当晶体管被编程时，绝缘体中的破裂很可能发生在重掺杂的聚硅氧烷栅极部分中。还公开了一种p沟道晶体管。

3. 发明申请

WO2012012512A1 ARRAY ARCHITECTURE FOR REDUCED VOLTAGE, LOW POWER SINGLE POLY EEPROM 审中-公开
标题翻译：用于降低电压，低功耗单个聚合物EEPROM的阵列架构
公开(公告)号：WO2012012512A1
公开(公告)日：2012-01-26
申请号：PCT/US2011/044651
申请日：2011-07-20
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , STIEGLER, Harvey, J. , MITCHELL, Allan, T.
发明人： STIEGLER, Harvey, J. , MITCHELL, Allan, T.
IPC分类号： G11C16/12 , G11C16/02
CPC分类号： G11C16/0441
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead (706) is connected to the switch of each memory cell in a first column. A bit line (718) is connected to the current path of each access transistor in the first column. A read select lead (721) is connected to a control terminal of each access transistor in the first row. A first row select lead (700) is connected to a control terminal of the switch in each memory cell in a first row.
摘要翻译：公开了电可擦除可编程只读存储器（EEPROM）存储器阵列（图7）。存储器阵列包括以行和列排列的多个存储单元。每个存储单元具有开关（714），存取晶体管（716）和感测晶体管（720）。每个存取晶体管的电流路径与每个相应感测晶体管的电流路径串联连接。第一程序数据引线（706）连接到第一列中的每个存储器单元的开关。位线（718）连接到第一列中每个存取晶体管的电流路径。读取选择引线（721）连接到第一行中的每个存取晶体管的控制端子。第一行选择引线（700）连接到第一行中的每个存储单元中的开关的控制端子。

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