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1. 发明申请

WO2013147878A1 PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR 审中-公开
标题翻译：在多处理器中基于预测的螺纹选择
公开(公告)号：WO2013147878A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031634
申请日：2012-03-30
申请人： INTEL CORPORATION , MERTEN, Matthew C. , LI, Tong , KADGI, Vijaykumar B. , SRINIVASAN, Srikanth T. , WANG, Christine E.
发明人： MERTEN, Matthew C. , LI, Tong , KADGI, Vijaykumar B. , SRINIVASAN, Srikanth T. , WANG, Christine E.
IPC分类号： G06F9/46 , G06F9/38 , G06F13/14
CPC分类号： G06F9/30145 , G06F9/3851 , G06F9/4843 , Y02D10/24
摘要： A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions.
摘要翻译：处理器包括一个或多个执行单元，用于执行多个线程的指令和与执行单元耦合的线程控制逻辑，以基于当前周期的指令的准备就绪来预测多个线程中的第一个线程是否准备好在当前周期中进行选择在一个或多个先前循环中的第一线程，以基于所述一个或多个先前循环中的第二线程的指令的准备来预测多个线程中的第二线程是否准备好在当前周期中进行选择，并且选择基于预测的当前循环中的第一和第二个线程。

2. 发明申请

WO2013100998A1 PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
标题翻译：具有分支机构错误预测的第二个执行单元的处理程序
公开(公告)号：WO2013100998A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067656
申请日：2011-12-28
申请人： INTEL CORPORATION , MERTEN, Matthew, C. , SODANI, Avinash , MIRKES, Sean, P. , KADGI, Vijaykumar, B. , SUTANTO, Bambang , LAI, Chia Yin, Kevin , MARDEN, Morris , FARCY, Alexandre, J.
发明人： MERTEN, Matthew, C. , SODANI, Avinash , MIRKES, Sean, P. , KADGI, Vijaykumar, B. , SUTANTO, Bambang , LAI, Chia Yin, Kevin , MARDEN, Morris , FARCY, Alexandre, J.
IPC分类号： G06F1/00 , G06F9/30 , G06F9/46
CPC分类号： G06F9/3844 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.
摘要翻译：次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而初级JEU不处理分支。此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

3. 发明申请

WO2014169032A1 SYSTEMS AND METHODS FOR FLAG TRACKING IN MOVE ELIMINATION OPERATIONS 审中-公开
标题翻译：标记跟踪在移动消除操作中的系统和方法
公开(公告)号：WO2014169032A1
公开(公告)日：2014-10-16
申请号：PCT/US2014/033486
申请日：2014-04-09
申请人： INTEL CORPORATION , KADGI, Vijaykumar B. , ANDERSON, Jeremy R. , HADLEY, James D. , LI, Tong , MERTEN, Matthew C.
发明人： KADGI, Vijaykumar B. , ANDERSON, Jeremy R. , HADLEY, James D. , LI, Tong , MERTEN, Matthew C.
IPC分类号： G06F9/06
CPC分类号： G06F9/30105 , G06F8/443 , G06F9/30032 , G06F9/30094 , G06F9/30098 , G06F9/3013 , G06F9/30181 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.
摘要翻译：涉及移动消除的数据处理操作中标志跟踪的系统和方法。示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

4. 发明申请

WO2013147895A2 DYNAMIC PHYSICAL REGISTER USE THRESHOLD ADJUSTMENT AND CROSS THREAD STALL IN MULTI-THREADED PROCESSORS 审中-公开
标题翻译：动态物理寄存器在多线程处理器中使用阈值调整和交叉螺纹
公开(公告)号：WO2013147895A2
公开(公告)日：2013-10-03
申请号：PCT/US2012/031710
申请日：2012-03-30
申请人： INTEL CORPORATION , HADLEY, James, D. , SRINIVASAN, Srikanth, T. , MERTEN, Matthew, C. , RAJWAR, Ravi, Rajwar , LIM, David, G. , ILYIN, Yury, N.
发明人： HADLEY, James, D. , SRINIVASAN, Srikanth, T. , MERTEN, Matthew, C. , RAJWAR, Ravi, Rajwar , LIM, David, G. , ILYIN, Yury, N.
CPC分类号： G06F9/3851 , G06F9/384 , G06F9/3891 , G06F9/5011 , G06F2209/504 , G06F2209/507 , Y02D10/22
摘要： A method in a processor of handling physical register use of an aspect includes determining that a first thread is attempting to enter a transitory higher physical register use mode. A physical register use threshold of a second thread is reduced from a higher physical register use threshold to a lower physical register use threshold, in response to the determination that the first thread is attempting to enter the transitory higher physical register use mode. It is determined that a physical register use value of the second thread is not within the lower physical register use threshold. The first thread is prevented from entering the transitory higher physical register use mode, while the physical register use value of the second thread is not within the lower physical register use threshold.
摘要翻译：处理器中处理方面的方法包括确定第一线程尝试进入短暂的较高物理寄存器使用模式。响应于确定第一线程尝试进入暂时性较高的物理寄存器使用模式，第二线程的物理寄存器使用阈值从较高物理寄存器使用阈值减小到较低物理寄存器使用阈值。确定第二线程的物理寄存器使用值不在较低的物理寄存器使用阈值内。第一个线程被阻止进入暂时更高的物理寄存器使用模式，而第二个线程的物理寄存器使用值不在较低的物理寄存器使用阈值内。

5. 发明申请

WO2013095529A1 ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS 审中-公开
标题翻译：附加说明独立进位链
公开(公告)号：WO2013095529A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066941
申请日：2011-12-22
申请人： INTEL CORPORATION , GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , FEGHALI, Wajdi K. , OZTURK, Erdinc , DIXON, Martin G. , MIRKES, Sean P. , MERTEN, Matthew C. , LI, Tong , TOLL, Bret L.
发明人： GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , FEGHALI, Wajdi K. , OZTURK, Erdinc , DIXON, Martin G. , MIRKES, Sean P. , MERTEN, Matthew C. , LI, Tong , TOLL, Bret L.
IPC分类号： G06F9/30 , G06F9/305 , G06F13/14
CPC分类号： G06F9/3001 , G06F9/30094 , G06F9/3838
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.
摘要翻译：提供了许多相互之间没有数据相关性的加法指令。第一加法指令将其进位输出存储在标志寄存器的第一标志中，而不修改标志寄存器中的第二标志。第二个加法指令将其进位输出存储在标志寄存器的第二个标志中，而不修改标志寄存器中的第一个标志。

6. 发明申请

WO2013147868A1 HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION 审中-公开
标题翻译：硬件配置机制启用页面级自动二进制翻译
公开(公告)号：WO2013147868A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031572
申请日：2012-03-30
申请人： INTEL CORPORATION , CAPRIOLI, Paul , MERTEN, Matthew C. , AL-OTOOM, Muawya M. , SHAIKH, Omar M. , KANHERE, Abhay S. , SRINIVAS, Suresh , YAMADA, Koichi , THAKKAR, Vivek , OSCIAK, Pawel
发明人： CAPRIOLI, Paul , MERTEN, Matthew C. , AL-OTOOM, Muawya M. , SHAIKH, Omar M. , KANHERE, Abhay S. , SRINIVAS, Suresh , YAMADA, Koichi , THAKKAR, Vivek , OSCIAK, Pawel
IPC分类号： G06F15/80 , G06F9/30 , G06F13/14
CPC分类号： G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
摘要： A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
摘要翻译：通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。运行期间的硬件标识内存中包含潜在优化指令的代码页。硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。

7. 发明申请

WO2013115818A1 A METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
标题翻译：用于交互式分析控制指令的方法，装置和系统
公开(公告)号：WO2013115818A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/023611
申请日：2012-02-02
申请人： INTEL CORPORATION , RAJWAR, Ravi , DIXON, Martin G. , LAI, Konrad K. , FARCY, Alexandre J. , TOLL, Bret L. , CHAPPELL, Robert S. , MERTEN, Matthew C. , PARTHASARATHY, Rajesh S. , HAMMARLUND, Per
发明人： RAJWAR, Ravi , DIXON, Martin G. , LAI, Konrad K. , FARCY, Alexandre J. , TOLL, Bret L. , CHAPPELL, Robert S. , MERTEN, Matthew C. , PARTHASARATHY, Rajesh S. , HAMMARLUND, Per
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30181 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3851 , G06F9/3859
摘要： An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similary provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.
摘要翻译：这里描述了一种用于提供猜测控制指令的装置和方法。提供xAcquire和xRelease指令来定义关键部分。在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。此外，xBegin和xEnd在指令集架构（ISA）中提供了类似的方式来定义事务代码区域。此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

8. 发明申请

WO2013100999A1 ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
标题翻译：启用和禁用分支机构错误预测的第二个执行单位
公开(公告)号：WO2013100999A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067658
申请日：2011-12-28
申请人： INTEL CORPORATION , DACHENE, Mark, J. , MERTEN, Matthew, C. , MIRKES, Sean, P.
发明人： DACHENE, Mark, J. , MERTEN, Matthew, C. , MIRKES, Sean, P.
IPC分类号： G06F1/00 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/3844 , G06F9/3851 , G06F9/3885
摘要： Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.
摘要翻译：描述了在微处理器中启用和/或禁用辅助跳转执行单元（JEU）的技术。次级JEU被并入微处理器以与主JEU同时操作，并且能够在多个分支上处理同时的分支错误预测。次级JEU的激活和停用可以由压力计数器或置信计数器来控制。压力计数器机构增加在处理器内执行的每个分支操作的计数，并在每个周期期间将计数减去衰减值。置信度计数机制增加每个正确预测分支的计数，并减少每个错误预测的计数。当计数器超过激活阈值时，每个计数器发出一个激活组件，例如端口绑定硬件组件，开始将微操作绑定到辅助JEU。计数器机制可能是线程不可知或线程特定的。

9. 发明申请

WO2006012103A3 METHOD AND APPARATUS FOR SPECULATIVE EXECUTION OF UNCONTENDED LOCK INSTRUCTIONS 审中-公开
公开(公告)号：WO2006012103A3
公开(公告)日：2006-02-02
申请号：PCT/US2005/021838
申请日：2005-06-17
申请人： INTEL CORPORATION , SAHA, Bratin , MERTEN, Matthew, C. , HAMMARLUND, Per
发明人： SAHA, Bratin , MERTEN, Matthew, C. , HAMMARLUND, Per
IPC分类号： G06F9/38
摘要： A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

10. 发明申请

WO2014004222A1 INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS 审中-公开
标题翻译：指令和逻辑测试交易执行状态
公开(公告)号：WO2014004222A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/046633
申请日：2013-06-19
申请人： INTEL CORPORATION , RAJWAR, Ravi , TOLL, Bret, L. , LAI, Konrad, K. , MERTEN, Matthew, C. , DIXON, Martin, G.
发明人： RAJWAR, Ravi , TOLL, Bret, L. , LAI, Konrad, K. , MERTEN, Matthew, C. , DIXON, Martin, G.
IPC分类号： G06F11/22
CPC分类号： G06F11/2236
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

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