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1. 发明申请

WO2006103563A8 METHOD AND APPARATUS FOR REDUCING SYSTEM INACTIVITY DURING TIME DATA FLOAT DELAY AND EXTERNAL MEMORY WRITE 审中-公开
标题翻译：在数据流延迟和外部存储器写入期间减少系统不活动的方法和装置
公开(公告)号：WO2006103563A8
公开(公告)日：2009-09-11
申请号：PCT/IB2006000957
申请日：2006-03-24
申请人： ATMEL CORP , MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
发明人： MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/405 , G06F13/4243
摘要： The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit (600) is coupled to an external peripheral by an external data bus (640). The integrated circuit (600) has a processor (605) coupled to an internal data bus (645). An external bus circuit (620) is coupled to the internal (645) and external data busses (640). The bus interface circuit (620) is configured to receive read and write signals for data request data, and then transmits a wait signal until data from the external periphera is available on the internal data bus (645), which indicates the external (640) and internal data busses (645) are unavailable. After the processor (605) receives or transmits the data, the bus interface circuit (620) stops transmitting the wait signal and transmits a busy signal, which indicates the internal data bus (645) is available and the external data bus (640) is unavailable.
摘要翻译：本发明包括用于减少集成电路中的非活动时段的系统。集成电路（600）通过外部数据总线（640）耦合到外部外围设备。集成电路（600）具有耦合到内部数据总线（645）的处理器（605）。外部总线电路（620）耦合到内部（645）和外部数据总线（640）。总线接口电路（620）被配置为接收用于数据请求数据的读取和写入信号，然后发送等待信号，直到来自外部周边的数据在内部数据总线（645）上可用，其指示外部（640）和内部数据总线（645）不可用。在处理器（605）接收或发送数据之后，总线接口电路（620）停止发送等待信号并发送指示内部数据总线（645）可用的忙信号，并且外部数据总线（640）是不可用。

2. 发明申请

WO2006112968A1 APPARATUS TO IMPROVE BANDWIDTH FOR CIRCUITS HAVING MULTIPLE MEMORY CONTROLLERS 审中-公开
标题翻译：改善具有多个存储器控制器的电路带宽的装置
公开(公告)号：WO2006112968A1
公开(公告)日：2006-10-26
申请号：PCT/US2006/008447
申请日：2006-03-08
申请人： ATMEL CORPORATION , MATULIK, Eric
发明人： MATULIK, Eric
IPC分类号： G06F13/00
CPC分类号： G06F13/1684
摘要： An apparatus (140) for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller (142) , a second memory controller (144) , a first busy read output signal circuit (146) , a first busy write output signal circuit (148) , a second busy read output signal circuit (156) , and a second busy write output signal circuit (154) . The first busy read output signal (8) indicates when the first memory controller (142) releases the address bus (166) for a next external access subsequent to a read access to the data bus by the first memory controller (142) . The first busy write output signal (7) indicates when the first memory controller (142) releases the data bus (162) for a next external access subsequent to a write access to the data bus by the first memory controller (142) . The second busy read output signal indicates when the second memory controller (144) releases the address bus (166) for a next external access subsequent to a read access to the data bus by the second memory controller (144) . The second busy write output signal (1) indicates when the second memory controller (144) releases the data bus (162) for a next external access subsequent to a write access to the data bus by the second memory controller (144) .
摘要翻译：一种用于改进具有采用第一存储器控制器（142）的多个存储控制器的电路的带宽的装置（140），第二存储器控制器（144），第一繁忙读输出信号电路（146），第一繁忙写输出信号电路（148），第二忙读输出信号电路（156）和第二忙写输出信号电路（154）。第一繁忙读输出信号（8）指示第一存储器控制器（142）何时释放用于第一存储器控制器（142）对数据总线的读访问之后的下一个外部访问的地址总线（166）。第一繁忙写入输出信号（7）指示在第一存储器控制器（142）对第一存储器控制器（142）对数据总线的写入之后，第一存储器控制器（142）何时释放用于下一个外部访问的数据总线（162）。第二繁忙读输出信号指示第二存储器控制器（144）何时释放用于第二存储器控制器（144）对数据总线的读访问之后的下一个外部访问的地址总线（166）。第二繁忙写入输出信号（1）指示第二存储器控制器（144）何时释放用于第二存储器控制器（144）对数据总线的写入访问之后的下一个外部访问的数据总线（162）。

3. 发明申请

WO2008024659A2 CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE 审中-公开
标题翻译：从存储设备中延迟信号的电路
公开(公告)号：WO2008024659A2
公开(公告)日：2008-02-28
申请号：PCT/US2007/076024
申请日：2007-08-15
申请人： ATMEL CORPORATION , MATULIK, Eric , VERGNES, Alain , SCHUMACHER, Frederic
发明人： MATULIK, Eric , VERGNES, Alain , SCHUMACHER, Frederic
IPC分类号： H01L27/10
CPC分类号： G06F13/1689
摘要： A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit.
摘要翻译：用于延迟输入控制信号的电路包括：时钟电路，用于生成具有与输入时钟信号不同的频率的时钟信号以延迟并且包括时钟信号输入;微分时钟信号输出; 用于编程其输入时钟频率与其输出时钟频率之间的频率比的输入。时钟捕捉电路提供确定数目的延迟元件，以提供由时钟电路提供的信号的周期量的延迟。延迟计算电路接收确定数量的延迟元件并计算将输入控制信号延迟一段时间所需的延迟元件的数量。延迟电路包括控制信号输入端，用于接收由延迟计算电路提供的多个延迟元件的选择输入端。

4. 发明申请

WO2006103563A2 METHOD AND APPARATUS FOR REDUCING SYSTEM INACTIVITY DURING TIME DATA FLOAT DELAY AND EXTERNAL MEMORY WRITE 审中-公开
标题翻译：在数据流延迟和外部存储器写入期间减少系统不活动的方法和装置
公开(公告)号：WO2006103563A2
公开(公告)日：2006-10-05
申请号：PCT/IB2006/000957
申请日：2006-03-24
申请人： ATMEL CORPORATION , MATULIK, Eric , RESCANIERES, Nicolas , LAFAGE, Anne
发明人： MATULIK, Eric , RESCANIERES, Nicolas , LAFAGE, Anne
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/405 , G06F13/4243
摘要： The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit is coupled to an external peripheral by an external data bus. The integrated circuit has a processor coupled to an internal data bus. The system comprises the following. An external bus circuit is coupled to the internal and external data busses. The bus interface circuit is configured to receive read and write signals for data request data. In response, the bus interfaces circuit transmits a wait signal until data from the external peripheral is available on the internal data bus. The wait signal indicates that the external and internal data busses are not available for other purposes. After the processor has received or transmits the data, the bus interface circuit stops transmitting the wait signal and transmits a busy signal. The busy signal indicates that the internal data bus is available and the external data bus is not available for other purposes.
摘要翻译：本发明包括用于减少集成电路中的非活动时段的系统。集成电路通过外部数据总线耦合到外部外围设备。集成电路具有耦合到内部数据总线的处理器。该系统包括以下。外部总线电路耦合到内部和外部数据总线。总线接口电路被配置为接收用于数据请求数据的读取和写入信号。作为响应，总线接口电路发送等待信号，直到来自外部外围设备的数据在内部数据总线上可用。等待信号表示外部和内部数据总线不可用于其他目的。处理器接收或发送数据后，总线接口电路停止发送等待信号并发送忙信号。忙信号表示内部数据总线可用，外部数据总线不可用于其他目的。

5. 发明申请

WO2008024680A2 CIRCUITS TO DELAY A SIGNAL FROM DDR-SDRAM MEMORY DEVICE INCLUDING AN AUTOMATIC PHASE ERROR CORRECTION 审中-公开
标题翻译：从DDR-SDRAM存储器设备中延迟信号的电路，包括自动相位误差校正
公开(公告)号：WO2008024680A2
公开(公告)日：2008-02-28
申请号：PCT/US2007076204
申请日：2007-08-17
申请人： ATMEL CORP , VERGNES ALAIN , MATULIK ERIC , SCHUMACHER FREDERIC
发明人： VERGNES ALAIN , MATULIK ERIC , SCHUMACHER FREDERIC
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C11/401 , G11C29/023 , G11C29/028 , G11C2029/0409
摘要： A method for delaying a control signal, comprises receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.
摘要翻译：一种用于延迟控制信号的方法，包括：接收时钟信号;确定产生等于时钟信号的周期的目标量的第一延迟所需的延迟元件的数量;接收具有在相同时间产生的边缘的数据信号时间确定为控制信号的边缘，确定一个分数数目等于产生数据信号的第二延迟所需的延迟元件的数量或控制信号的对准其边缘所需的数量除以提供必要的级联延迟元件的数量等于时钟信号的周期的目标量的延迟乘以延迟元件的数量以产生第一延迟，并且将控制信号延迟级联延迟元件的数量以实现由分数编号改变的所述第一延迟的延迟元素。

6. 发明申请

WO2006103563A3 METHOD AND APPARATUS FOR REDUCING SYSTEM INACTIVITY DURING TIME DATA FLOAT DELAY AND EXTERNAL MEMORY WRITE 审中-公开
标题翻译：在数据流延迟和外部存储器写入期间减少系统不活动的方法和装置
公开(公告)号：WO2006103563A3
公开(公告)日：2007-04-26
申请号：PCT/IB2006000957
申请日：2006-03-24
申请人： ATMEL CORP , MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
发明人： MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/405 , G06F13/4243
摘要： The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit (600) is coupled to an external peripheral by an external data bus (640). The integrated circuit (600) has a processor (605) coupled to an internal data bus (645). An external bus circuit (620) is coupled to the internal (645) and external data busses (640). The bus interface circuit (620) is configured to receive read and write signals for data request data, and then transmits a wait signal until data from the external periphera is available on the internal data bus (645), which indicates the external (640) and internal data busses (645) are unavailable. After the processor (605) receives or transmits the data, the bus interface circuit (620) stops transmitting the wait signal and transmits a busy signal, which indicates the internal data bus (645) is available and the external data bus (640) is unavailable.
摘要翻译：本发明包括用于减少集成电路中的非活动时段的系统。集成电路（600）通过外部数据总线（640）耦合到外部外围设备。集成电路（600）具有耦合到内部数据总线（645）的处理器（605）。外部总线电路（620）耦合到内部（645）和外部数据总线（640）。总线接口电路（620）被配置为接收用于数据请求数据的读取和写入信号，然后发送等待信号，直到来自外部周边的数据在内部数据总线（645）上可用，其指示外部（640）和内部数据总线（645）不可用。在处理器（605）接收或发送数据之后，总线接口电路（620）停止发送等待信号并发送指示内部数据总线（645）可用的忙信号，并且外部数据总线（640）是不可用。

7. 发明申请

WO2008094968A3 CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER 审中-公开
公开(公告)号：WO2008094968A3
公开(公告)日：2008-08-07
申请号：PCT/US2008/052405
申请日：2008-01-30
申请人： ATMEL CORPORATION , VERGNES, Alain , MATULIK, Eric , SCHUMACHER, Frederic
发明人： VERGNES, Alain , MATULIK, Eric , SCHUMACHER, Frederic
IPC分类号： G11C8/16
摘要： A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.

8. 发明申请

WO2008094968A2 CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER 审中-公开
标题翻译： DDR SDRAM内存控制器的时钟电路
公开(公告)号：WO2008094968A2
公开(公告)日：2008-08-07
申请号：PCT/US2008052405
申请日：2008-01-30
申请人： ATMEL CORP , VERGNES ALAIN , MATULIK ERIC , SCHUMACHER FREDERIC
发明人： VERGNES ALAIN , MATULIK ERIC , SCHUMACHER FREDERIC
CPC分类号： G06F13/4243 , G06F13/1689
摘要： A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.
摘要翻译：用于向控制同步存储器件的同步存储器控制器提供延迟时钟信号的电路包括用于执行同步存储器件读取访问的逻辑延迟电路，逻辑延迟电路产生延迟间隔信息。可编程延迟线接收时钟信号和延迟间隔信息，可编程延迟线将时钟信号延迟延迟时间间隔。 2输入XOR门接收时钟信号和可编程延迟线的输出，XOR门的输出提供延迟的2X时钟信号。

9. 发明申请

WO2008024659A3 CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE 审中-公开
标题翻译：电路延迟信号从记忆设备
公开(公告)号：WO2008024659A3
公开(公告)日：2008-06-26
申请号：PCT/US2007076024
申请日：2007-08-15
申请人： ATMEL CORP , MATULIK ERIC , VERGNES ALAIN , SCHUMACHER FREDERIC
发明人： MATULIK ERIC , VERGNES ALAIN , SCHUMACHER FREDERIC
IPC分类号： H03L7/00
CPC分类号： G06F13/1689
摘要： A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit.
摘要翻译：一种用于延迟输入控制信号的电路，包括时钟电路，用于产生具有不同于输入时钟信号的频率的时钟信号以延迟并包括时钟信号输入，微分时钟信号输出，输入以编程输入控制信号之间的频率比其输入时钟频率及其输出时钟频率。时钟捕获电路提供确定数量的延迟元件，以提供由时钟电路提供的信号的周期的量的延迟。延迟计算电路接收确定数量的延迟元件，并计算延迟输入控制信号所需时间的延迟元件的数量。延迟电路包括控制信号输入，用于接收由延迟计算电路提供的延迟元件的数量的选择输入。

10. 发明申请

WO2008048835A1 READ-DATA STAGE CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER 审中-公开
标题翻译： DDR-SDRAM存储器控制器的读取数据级电路
公开(公告)号：WO2008048835A1
公开(公告)日：2008-04-24
申请号：PCT/US2007/080934
申请日：2007-10-10
申请人： ATMEL CORPORATION , VERGNES, Alain , MATULIK, Eric
发明人： VERGNES, Alain , MATULIK, Eric
IPC分类号： G11C7/10
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093
摘要： A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of the data bus carrying data provided by the memory device at a period being an integer multiple of the clock signal where the sampling point is different for each sub-part.
摘要翻译：用于从存储器件采样数据的电路包括用于向存储器件提供时钟信号的电路，一个以时钟信号速率的两倍传送数据的数据总线，一个电路，用于提供一个控制信号，以指示一段时间，数据是有效的，还有一组寄存器，其内容由控制信号的延迟产生的信号的两个边沿触发。该寄存器组被分成若干个子部分，每个子部分载入数据总线的值，该数据总线承载存储器件提供的数据的周期是时钟信号的整数倍，每个子采样点不同 -部分。

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