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1. 发明申请

WO2008024680A2 CIRCUITS TO DELAY A SIGNAL FROM DDR-SDRAM MEMORY DEVICE INCLUDING AN AUTOMATIC PHASE ERROR CORRECTION 审中-公开
标题翻译：从DDR-SDRAM存储器设备中延迟信号的电路，包括自动相位误差校正
公开(公告)号：WO2008024680A2
公开(公告)日：2008-02-28
申请号：PCT/US2007076204
申请日：2007-08-17
申请人： ATMEL CORP , VERGNES ALAIN , MATULIK ERIC , SCHUMACHER FREDERIC
发明人： VERGNES ALAIN , MATULIK ERIC , SCHUMACHER FREDERIC
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C11/401 , G11C29/023 , G11C29/028 , G11C2029/0409
摘要： A method for delaying a control signal, comprises receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.
摘要翻译：一种用于延迟控制信号的方法，包括：接收时钟信号;确定产生等于时钟信号的周期的目标量的第一延迟所需的延迟元件的数量;接收具有在相同时间产生的边缘的数据信号时间确定为控制信号的边缘，确定一个分数数目等于产生数据信号的第二延迟所需的延迟元件的数量或控制信号的对准其边缘所需的数量除以提供必要的级联延迟元件的数量等于时钟信号的周期的目标量的延迟乘以延迟元件的数量以产生第一延迟，并且将控制信号延迟级联延迟元件的数量以实现由分数编号改变的所述第一延迟的延迟元素。

2. 发明申请

WO2008024659A2 CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE 审中-公开
标题翻译：从存储设备中延迟信号的电路
公开(公告)号：WO2008024659A2
公开(公告)日：2008-02-28
申请号：PCT/US2007/076024
申请日：2007-08-15
申请人： ATMEL CORPORATION , MATULIK, Eric , VERGNES, Alain , SCHUMACHER, Frederic
发明人： MATULIK, Eric , VERGNES, Alain , SCHUMACHER, Frederic
IPC分类号： H01L27/10
CPC分类号： G06F13/1689
摘要： A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit.
摘要翻译：用于延迟输入控制信号的电路包括：时钟电路，用于生成具有与输入时钟信号不同的频率的时钟信号以延迟并且包括时钟信号输入;微分时钟信号输出; 用于编程其输入时钟频率与其输出时钟频率之间的频率比的输入。时钟捕捉电路提供确定数目的延迟元件，以提供由时钟电路提供的信号的周期量的延迟。延迟计算电路接收确定数量的延迟元件并计算将输入控制信号延迟一段时间所需的延迟元件的数量。延迟电路包括控制信号输入端，用于接收由延迟计算电路提供的多个延迟元件的选择输入端。

3. 发明申请

WO2008094968A3 CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER 审中-公开
公开(公告)号：WO2008094968A3
公开(公告)日：2008-08-07
申请号：PCT/US2008/052405
申请日：2008-01-30
申请人： ATMEL CORPORATION , VERGNES, Alain , MATULIK, Eric , SCHUMACHER, Frederic
发明人： VERGNES, Alain , MATULIK, Eric , SCHUMACHER, Frederic
IPC分类号： G11C8/16
摘要： A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.

4. 发明申请

WO2008094968A2 CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER 审中-公开
标题翻译： DDR SDRAM内存控制器的时钟电路
公开(公告)号：WO2008094968A2
公开(公告)日：2008-08-07
申请号：PCT/US2008052405
申请日：2008-01-30
申请人： ATMEL CORP , VERGNES ALAIN , MATULIK ERIC , SCHUMACHER FREDERIC
发明人： VERGNES ALAIN , MATULIK ERIC , SCHUMACHER FREDERIC
CPC分类号： G06F13/4243 , G06F13/1689
摘要： A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.
摘要翻译：用于向控制同步存储器件的同步存储器控制器提供延迟时钟信号的电路包括用于执行同步存储器件读取访问的逻辑延迟电路，逻辑延迟电路产生延迟间隔信息。可编程延迟线接收时钟信号和延迟间隔信息，可编程延迟线将时钟信号延迟延迟时间间隔。 2输入XOR门接收时钟信号和可编程延迟线的输出，XOR门的输出提供延迟的2X时钟信号。

5. 发明申请

WO2008024659A3 CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE 审中-公开
标题翻译：电路延迟信号从记忆设备
公开(公告)号：WO2008024659A3
公开(公告)日：2008-06-26
申请号：PCT/US2007076024
申请日：2007-08-15
申请人： ATMEL CORP , MATULIK ERIC , VERGNES ALAIN , SCHUMACHER FREDERIC
发明人： MATULIK ERIC , VERGNES ALAIN , SCHUMACHER FREDERIC
IPC分类号： H03L7/00
CPC分类号： G06F13/1689
摘要： A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit.
摘要翻译：一种用于延迟输入控制信号的电路，包括时钟电路，用于产生具有不同于输入时钟信号的频率的时钟信号以延迟并包括时钟信号输入，微分时钟信号输出，输入以编程输入控制信号之间的频率比其输入时钟频率及其输出时钟频率。时钟捕获电路提供确定数量的延迟元件，以提供由时钟电路提供的信号的周期的量的延迟。延迟计算电路接收确定数量的延迟元件，并计算延迟输入控制信号所需时间的延迟元件的数量。延迟电路包括控制信号输入，用于接收由延迟计算电路提供的延迟元件的数量的选择输入。

6. 发明申请

WO2008024680A3 CIRCUITS TO DELAY A SIGNAL FROM DDR-SDRAM MEMORY DEVICE INCLUDING AN AUTOMATIC PHASE ERROR CORRECTION 审中-公开
公开(公告)号：WO2008024680A3
公开(公告)日：2008-02-28
申请号：PCT/US2007/076204
申请日：2007-08-17
申请人： ATMEL CORPORATION , VERGNES, Alain , MATULIK, Eric , SCHUMACHER, Frederic
发明人： VERGNES, Alain , MATULIK, Eric , SCHUMACHER, Frederic
IPC分类号： G11C8/00
摘要： A method for delaying a control signal, comprises receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.

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