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1. 发明申请

WO2015061596A4 UNIFIED CONNECTOR FOR MULTIPLE INTERFACES 审中-公开
标题翻译：用于多个接口的统一连接器
公开(公告)号：WO2015061596A4
公开(公告)日：2016-01-07
申请号：PCT/US2014062015
申请日：2014-10-23
申请人： APPLE INC
发明人： CORNELIUS WILLIAM P , BAKER PAUL A , FERRY WILLIAM O , KIM MIN CHUL , NG NATHAN N
IPC分类号： G06F13/40 , G01D5/12
CPC分类号： H01B7/0009 , G01D5/12 , G06F13/405 , H01B9/006 , H01B11/1891 , H01B11/20 , H03L9/00
摘要： Circuits, methods, and apparatus that may reduce the number of connector receptacles that are needed on an electronic device. One example may provide a unified connector and circuitry that may be capable of communicating with more than one interface.
摘要翻译：可减少电子设备所需的连接器插座数量的电路，方法和设备。一个示例可以提供可以与多于一个接口通信的统一的连接器和电路。

2. 发明申请

WO2015116037A1 MANAGING A MULTI-LANE SERIAL LINK 审中-公开
标题翻译：管理多个串行链路
公开(公告)号：WO2015116037A1
公开(公告)日：2015-08-06
申请号：PCT/US2014/013419
申请日：2014-01-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： LESARTRE, Gregg B. , FOLTIN, Martin
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/405 , Y02D10/14 , Y02D10/151
摘要： A method for managing a multi-lane serial link is described. The method includes establishing a serial link between a number of integrated circuits across a first number of lanes. The first number of lanes are a subset of a number of available lanes on the serial link. The method also includes selecting to change a transmission state of a second number of lanes. The second number of lanes are a subset of the available lanes. The method also includes changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes. The method further includes synchronizing the first number of lanes and the second number of lanes.
摘要翻译：描述了一种用于管理多通道串行链路的方法。该方法包括在多个通道之间的多个集成电路之间建立串行链路。第一条车道是串行链路上可用车道数量的一个子集。该方法还包括选择改变第二数量车道的传输状态。第二条车道是可用车道的一个子集。该方法还包括改变第二数量车道的传输状态，同时在多条剩余车道上传送数据。该方法还包括使第一数量的车道和第二车道数量同步。

3. 发明申请

WO2014070651A1 OPERATING M-PHY BASED COMMUNICATIONS OVER PCI-BASED INTERFACES, AND RELATED CABLES, CONNECTORS, SYSTEMS AND METHODS 审中-公开
标题翻译：基于PCI接口的基于M-PHY的通信，相关电缆，连接器，系统和方法
公开(公告)号：WO2014070651A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/067049
申请日：2013-10-28
申请人： QUALCOMM INCORPORATED
发明人： HERSHKO, Yuval Corey , RIMONI, Yoram
IPC分类号： G06F13/38
CPC分类号： G06F13/387 , G06F13/385 , G06F13/405
摘要： Embodiments disclosed herein include operating the M-PHY communications over peripheral component interconnect (PCI)-based interfaces. Related cables, connectors, systems, and methods are also disclosed. In particular, embodiments disclosed herein take the M-PHY standard compliant signals and direct them through a PCI compliant connector (and optionally cable) so as to allow two M-PHY standard compliant devices having PCI connectors to communicate.
摘要翻译：本文公开的实施例包括通过基于外围组件互连（PCI）的接口来操作M-PHY通信。还公开了相关的电缆，连接器，系统和方法。特别地，本文公开的实施例采用符合M-PHY标准的信号，并将它们引导通过PCI兼容连接器（以及可选地电缆），以允许具有PCI连接器的两个符合M-PHY标准的设备进行通信。

4. 发明申请

WO2010132941A1 UNIVERSAL TIME-BASED EXTENSIONS FOR INSTRUMENTATION 审中-公开
标题翻译：通用的基于时间的仪器扩展
公开(公告)号：WO2010132941A1
公开(公告)日：2010-11-25
申请号：PCT/AU2010/000602
申请日：2010-05-20
申请人： CHRONOLOGIC PTY. LTD. , FOSTER, Peter Graham
发明人： FOSTER, Peter Graham
IPC分类号： G06F1/10 , G06F1/04 , H04L7/04
CPC分类号： G06F13/423 , G06F1/08 , G06F1/12 , G06F11/3027 , G06F13/10 , G06F13/4022 , G06F13/4027 , G06F13/405 , G06F13/4282 , G06F2213/0042 , H04L7/04 , H04L7/08
摘要： A method of controlling a plurality of event driven instruments as a single time- controlled synchronous virtual instrument, the method comprising: attaching the plurality of instruments to a common communications network; attaching a control device to the common communication network, the control device containing a local clock, the local clock maintaining a notion of real time; providing the control device with a plurality of trigger times, each of the trigger times associated with one or more of the instruments; and transmitting an event signal to those of the instruments associated with a respective one of the trigger times when the notion of real time of the control device matches the respective trigger time.
摘要翻译：一种将多个事件驱动仪器控制为单个时间控制同步虚拟仪器的方法，所述方法包括：将所述多个仪器附接到公共通信网络; 将控制装置附加到公共通信网络，控制装置包含本地时钟，本地时钟保持实时的概念; 向控制设备提供多个触发时间，每个触发时间与一个或多个仪器相关联; 以及当控制装置的实时概念与相应的触发时间匹配时，将事件信号发送到与相应的触发时间相关联的仪器的事件信号。

5. 发明申请

WO2010132938A1 COMPOUND UNIVERSAL SERIAL BUS ARCHITECTURE PROVIDING PRECISION SYNCHRONISATION TO AN EXTERNAL TIMEBASE 审中-公开
标题翻译：化学通用串行总线架构提供精确同步到外部时基
公开(公告)号：WO2010132938A1
公开(公告)日：2010-11-25
申请号：PCT/AU2010/000599
申请日：2010-05-20
申请人： CHRONOLOGIC PTY. LTD. , FOSTER, Peter Graham
发明人： FOSTER, Peter Graham
IPC分类号： G06F1/12 , G06F13/42 , H04L7/00
CPC分类号： G06F13/423 , G06F1/08 , G06F1/12 , G06F11/3027 , G06F13/10 , G06F13/4022 , G06F13/4027 , G06F13/405 , G06F13/4282 , G06F2213/0042 , H04L7/04 , H04L7/08
摘要： A method of synchronising a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronisation channel to a non-Super Speed USB function of the compound USB device; and synchronising a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronisation channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.
摘要翻译：一种同步复合超速USB设备的方法，包括：通过超速USB通信信道在主机计算设备和复合超速USB设备之间提供数据通信; 建立超级USB通信通道，实现复合USB设备的超速USB功能; 建立一个非超级速度同步通道，用于复合USB设备的非超速USB功能; 以及将所述复合USB设备的本地时钟同步到所述非超级速度同步信道中的数据流内的周期性数据结构，使得所述本地时钟能够启用所述复合USB设备与一个或多个可比USB设备的同步操作。

6. 发明申请

WO2006103563A3 METHOD AND APPARATUS FOR REDUCING SYSTEM INACTIVITY DURING TIME DATA FLOAT DELAY AND EXTERNAL MEMORY WRITE 审中-公开
标题翻译：在数据流延迟和外部存储器写入期间减少系统不活动的方法和装置
公开(公告)号：WO2006103563A3
公开(公告)日：2007-04-26
申请号：PCT/IB2006000957
申请日：2006-03-24
申请人： ATMEL CORP , MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
发明人： MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/405 , G06F13/4243
摘要： The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit (600) is coupled to an external peripheral by an external data bus (640). The integrated circuit (600) has a processor (605) coupled to an internal data bus (645). An external bus circuit (620) is coupled to the internal (645) and external data busses (640). The bus interface circuit (620) is configured to receive read and write signals for data request data, and then transmits a wait signal until data from the external periphera is available on the internal data bus (645), which indicates the external (640) and internal data busses (645) are unavailable. After the processor (605) receives or transmits the data, the bus interface circuit (620) stops transmitting the wait signal and transmits a busy signal, which indicates the internal data bus (645) is available and the external data bus (640) is unavailable.
摘要翻译：本发明包括用于减少集成电路中的非活动时段的系统。集成电路（600）通过外部数据总线（640）耦合到外部外围设备。集成电路（600）具有耦合到内部数据总线（645）的处理器（605）。外部总线电路（620）耦合到内部（645）和外部数据总线（640）。总线接口电路（620）被配置为接收用于数据请求数据的读取和写入信号，然后发送等待信号，直到来自外部周边的数据在内部数据总线（645）上可用，其指示外部（640）和内部数据总线（645）不可用。在处理器（605）接收或发送数据之后，总线接口电路（620）停止发送等待信号并发送指示内部数据总线（645）可用的忙信号，并且外部数据总线（640）是不可用。

7. 发明申请

WO2005106687A1 CIRCUIT WITH ASYNCHRONOUS/SYNCHRONOUS INTERFACE 审中-公开
标题翻译：具有异步/同步接口的电路
公开(公告)号：WO2005106687A1
公开(公告)日：2005-11-10
申请号：PCT/IB2005/051360
申请日：2005-04-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TIMMERMANS, Daniel
发明人： TIMMERMANS, Daniel
IPC分类号： G06F13/40
CPC分类号： G06F13/405
摘要： Data is communicated between an asynchronously operating circuit (10) and a clocked operating sub-circuit (16, 17). A data signal is supplied from the asynchronously operating sub-circuit (10) accompanied by a blocking/non blocking control signal. A request signal from the asynchronously operating sub-circuit (10) when the data signal and the control signal are being supplied. The data is stored in response to the request at least if the control signal supplied with the data has a first value. The request signal is routed through a path through handshake elements in a handshake circuit (20, 30,40) that is arranged to generate an acknowledge signal in response to the request signal to the asynchronously operating sub-circuit (10). The path through the handshake elements dependent on the control signal, so that the acknowledge signal is generated upon storing the data signal that accompanies the request at the output into the storage element when the control signal supplied with the data has the first value, and the acknowledge signal is generated upon detecting a clock cycle of the clocked operating sub-circuit wherein the clocked operating sub-circuit accepts the data that accompanies the request when the control signal has a second value.
摘要翻译：数据在异步操作电路（10）和时钟操作子电路（16,17）之间通信。数据信号由异步操作子电路（10）提供，伴随着阻塞/非阻塞控制信号。当提供数据信号和控制信号时来自异步操作子电路（10）的请求信号。至少如果提供有数据的控制信号具有第一值，则响应于该请求存储数据。所述请求信号通过路径通过握手电路（20,30,40）中的握手元件路由，所述握手电路被布置为响应于所述异步操作子电路（10）的请求信号而产生确认信号。通过握手元件的路径取决于控制信号，使得当提供有数据的控制信号具有第一值时，在将输出中伴随请求的数据信号存储到存储元件中时产生确认信号，并且在检测到时钟操作子电路的时钟周期时产生确认信号，其中当控制信号具有第二值时，时钟操作子电路接受伴随该请求的数据。

8. 发明申请

WO0231664A3 SYSTEM, METHOD AND ARTICLE OF MANUFACTURE FOR DATA TRANSFER ACROSS CLOCK DOMAINS 审中-公开
标题翻译：用于数据传输的系统，方法和文章通过时钟域
公开(公告)号：WO0231664A3
公开(公告)日：2003-05-01
申请号：PCT/GB0104538
申请日：2001-10-11
申请人： CELOXICA LTD , BOWEN MATT
发明人： BOWEN MATT
IPC分类号： G06F5/06 , G06F13/40 , G06F17/50
CPC分类号： G06F5/06 , G06F13/405
摘要： A system, method and article of manufacture are provided for data transfer across different clock domains. A request for transferring data from a sending (transmitting) process in a first domain to a receiving process in a second domain is received. The first domain and the second domain have different clocks. A channel circuit is created with handshaking and resynchoronization logic to help resolve metastability. The channel circuit is then used to transfer the data from the sending process to the receiving process.
摘要翻译：提供了用于不同时钟域的数据传输的系统，方法和制造。接收从第一域中的发送（发送）处理将数据传送到第二域中的接收处理的请求。第一个域和第二个域具有不同的时钟。创建一个通道电路，具有握手和重新放电逻辑，以帮助解决亚稳态。然后，通道电路用于将数据从发送过程传送到接收过程。

9. 发明申请

WO0142936A2 TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY 审中-公开
标题翻译：具有延迟对准电路的收发器
公开(公告)号：WO0142936A2
公开(公告)日：2001-06-14
申请号：PCT/US0041554
申请日：2000-10-24
申请人： RAMBUS INC
发明人： DONNELLY KEVIN , JOHNSON MARK , TRAN CHANH
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.
摘要翻译：描述收发器系统。次存储器模块耦合到主信道，用于从控制器接收数据和信号。辅助存储器模块包括用于将数据和控制信号发送到存储器的存储器和辅助通道。次存储器模块还包括耦合到主信道和次信道的收发器。收发器被设计为将次级通道与主通道电隔离。收发器是一个低延迟中继器，允许来自控制器的数据和控制信号到达存储器，使得来自控制器的数据请求的等待时间与收发器与控制器的距离无关。

10. 发明申请

WO1998013768A2 INTERFACE FOR TRANSFERRING DATA BETWEEN TWO CLOCK DOMAINS 审中-公开
标题翻译：用于传输两个时钟域之间的数据接口
公开(公告)号：WO1998013768A2
公开(公告)日：1998-04-02
申请号：PCT/IB1997001151
申请日：1997-09-25
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , JACOBS, Eino
IPC分类号： G06F13/42
CPC分类号： G06F9/30141 , G06F13/405 , H04L7/0012 , H04L7/02
摘要： An interface between two clock domains transfers data between the two clock domains without corruption or loss of data being transferred. Each clock domain has a respective clock. A synchronization circuit ensures that the two clocks have a fixed frequency ratio A:B and produces two synchronization signals which identify initial cycles of the clocks in underlying cycles of A and B clock cycles of the two clocks respectively. A data signal is registered in a plurality of registers in the first clock domain. Each register outputs a specific output signal, one of which is selected by a multiplexer in the second clock domain, to be output to an output register. The output register then outputs the data in synchronism with the second clock. Selection of the clock cycles in which reading and writing of a register takes place is controlled by the synchronization signals, so that there is a minimum delay between reading and writing even when there is a skew between the two clocks.
摘要翻译：两个时钟域之间的接口在两个时钟域之间传输数据，而不会损坏或丢失正在传输的数据。每个时钟域都有一个相应的时钟。同步电路确保两个时钟具有固定的频率比A：B，并产生两个同步信号，分别标识两个时钟的A和B时钟周期的基本周期中的时钟的初始周期。数据信号被登记在第一时钟域中的多个寄存器中。每个寄存器输出特定的输出信号，其中一个输出信号由第二个时钟域中的多路复用器选择，以输出到输出寄存器。输出寄存器然后与第二个时钟同步输出数据。通过同步信号控制寄存器的读取和写入的时钟周期的选择，使得即使在两个时钟之间存在偏斜的情况下，读取和写入之间也存在最小的延迟。

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