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1. 发明申请

WO1997008593A1 NUMERICAL CONTROLLER 审中-公开
标题翻译：数控系统
公开(公告)号：WO1997008593A1
公开(公告)日：1997-03-06
申请号：PCT/JP1996002338
申请日：1996-08-21
申请人： FANUC LTD , KINOSHITA, Jiro , AOYAMA, Kazunari , KUBO, Yoshiyuki , OKAMURA, Yukio
发明人： FANUC LTD
IPC分类号： G05B19/18
CPC分类号： G05B19/39 , G05B19/19 , G05B2219/33187 , G05B2219/33244 , G05B2219/37297 , G05B2219/41003 , G05B2219/41068
摘要： A numerical controller is provided with a machine-side position detection control unit (20) so as to read the position feedback signal of a position detector (64) for a control axis (X-axis) the position of which is required to be detected on the machine side for closed-loop control. Therefore, position detection control units for the servo amplifier sections (30, 40, and 50) on the axes is unnecessary. A numerical control section (10) is connected to the servo amplifier sections (30, 40, and 50) through a serial communication line in the form of a daisy chain.
摘要翻译：数字控制器设置有机器侧位置检测控制单元（20），以便读取其位置需要检测的控制轴（X轴）的位置检测器（64）的位置反馈信号在机器侧进行闭环控制。因此，不需要在轴上的伺服放大器部（30,40和50）的位置检测控制单元。数字控制部分（10）通过菊花链形式的串行通信线路连接到伺服放大器部分（30,40和50）。

2. 发明申请

WO1989008288A1 NUMERIC CONTROL UNIT FOR MULTIPLE-SPINDLE AND MULTIPLE-SYSTEM MACHINE TOOL 审中-公开
标题翻译：多主动和多系统机床工具的数字控制单元
公开(公告)号：WO1989008288A1
公开(公告)日：1989-09-08
申请号：PCT/JP1989000157
申请日：1989-02-16
申请人： FANUC LTD , KURAKAKE, Mitsuo , KINOSHITA, Jiro
发明人： FANUC LTD
IPC分类号： G05B19/18
CPC分类号： G05B19/4142 , G05B19/4141 , G05B2219/33163 , G05B2219/33167 , G05B2219/33168 , G05B2219/33338 , G05B2219/34013
摘要： This invention relates to a numeric control unit for a multiple-spindle and multiple-system machine tool wherein a plurality of spindles are controlled by a plurality of systems. A main processor (1) for executing data processing other than those of a servo system and an operator interface module (2) are connected to a first bus (7). A plurality of servo command generation processors (10, 20, 30) for generating input data processing and servo commands for each channel are connected to the first bus (7) and to a second bus (41). A plurality of servo control processors (42 to 45) are connected to the second bus (41) and transfers only the servo command data. The first bus (7) transfers the data other than those described above. In this manner, the generation of the servo commands can be processed at a high speed and a high-speed control of a multiple-spindle and multiple-system machine tool can be accomplished.

3. 发明申请

WO1989002126A1 DMA CONTROL SYSTEM 审中-公开
标题翻译： DMA控制系统
公开(公告)号：WO1989002126A1
公开(公告)日：1989-03-09
申请号：PCT/JP1988000822
申请日：1988-08-18
申请人： FANUC LTD , KINOSHITA, Jiro
发明人： FANUC LTD
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA control system for controlling the data transfer in the numerical controller and the like. A DMA control circuit (12) reads address data from a DMA address memory (14) storing address data, carries out the calculation, and transfers the calculated address data as a transfer address to execute the DMA control. Therefore, the DMA control is carried out even when the arrangement of the data in the sending portion and that of the data in the receiving portion are not in sequential correspondence.
摘要翻译：用于控制数字控制器等中的数据传送的DMA控制系统。 DMA控制电路（12）从存储地址数据的DMA地址存储器（14）读取地址数据，进行计算，并将所计算的地址数据作为传送地址传送，以执行DMA控制。因此，即使发送部分中的数据的布置和接收部分中的数据的布置不是顺序对应的，也执行DMA控制。

4. 发明申请

WO1989002105A1 NUMERICAL CONTROLLER 审中-公开
标题翻译：数控系统
公开(公告)号：WO1989002105A1
公开(公告)日：1989-03-09
申请号：PCT/JP1988000848
申请日：1988-08-25
申请人： FANUC LTD , KURAKAKE, Mitsuo , KINOSHITA, Jiro
发明人： FANUC LTD
IPC分类号： G05B19/403
CPC分类号： G05B19/4148 , G05B2219/33156 , G05B2219/34076
摘要： A numerical controller which controls a numerically controlled machine tool utilizing resources connected to the system bus. An additional processor is connected to the system bus to execute a predetermined task in order to assist the processing ability of the CPU. The CPU and the additional processor are not simply interfaced through the external bus but are directly connected to each other through a special interactive memory in order to enhance the numerical control capacity without decreasing the efficiency of utilizing resources in the CPU.

5. 发明申请

WO1989002104A1 SPINDLE CONTROL METHOD AND NUMERICAL CONTROLLER 审中-公开
标题翻译：主轴控制方法和数控系统
公开(公告)号：WO1989002104A1
公开(公告)日：1989-03-09
申请号：PCT/JP1988000875
申请日：1988-08-31
申请人： FANUC LTD , KURAKAKE, Mitsuo , KINOSHITA, Jiro
发明人： FANUC LTD
IPC分类号： G05B19/18
CPC分类号： G05B19/232 , G05B19/186 , G05B2219/37135 , G05B2219/37154 , G05B2219/37297 , G05B2219/42104
摘要： A spindle control method for a numerical controller (CNC). A microprocessor (11), a memory (12), and two counters (13, 15) for counting pulses from encoders form a servo control circuit (10) which is connected to a CNC bus (1). There are provided a power amplifier (21) for controlling the rotation of the spindle motor upon receiving an instruction from the servo control circuit (10), and a separate encoder (25) coupled to the spindle for feeding pulses back to the counter (13) to control the profile. One counter (13) of the servo control circuit (10) is used for detecting the rotation position of the spindle motor (22) and another counter (15) counts the pulses that are fed back for operations such as threading. Therefore, the spindle motor (22) is controlled for its position and rotations by the servo control circuit (10).

6. 发明申请

WO1988009535A1 PROCESSOR CONTROL SYSTEM 审中-公开
标题翻译：处理器控制系统
公开(公告)号：WO1988009535A1
公开(公告)日：1988-12-01
申请号：PCT/JP1988000468
申请日：1988-05-17
申请人： FANUC LTD , KINOSHITA, Jiro
发明人： FANUC LTD
IPC分类号： G06F09/32
CPC分类号： G06F9/3802
摘要： A processor control system having a plurality of memories (5, 6, 7). A microprocessor (1) is provided with an ordinary address bus (2), a data bus (3), and a dedicated instruction read bus (4) connected with an instruction memory (5). Since the instruction read bus (4) is provided, the processor (1) executes the instruction while reading the instruction from the instruction read bus (4). Therefore, the processor (1) can operate at an increased speed.
摘要翻译：一种具有多个存储器（5,6,7）的处理器控制系统。微处理器（1）具有与指令存储器（5）连接的普通地址总线（2），数据总线（3）和专用指令读总线（4）。由于提供了指令读取总线（4），处理器（1）在读取来自指令读取总线（4）的指令的同时执行指令。因此，处理器（1）可以以增加的速度运行。

7. 发明申请

WO1988004452A1 PROCESSING UNIT HAVING AT LEAST ONE COPROCESSOR 审中-公开
标题翻译：加工单位至少有一个合作者
公开(公告)号：WO1988004452A1
公开(公告)日：1988-06-16
申请号：PCT/JP1987000943
申请日：1987-12-07
申请人： FANUC LTD , KURAKAKE, Mitsuo , KINOSHITA, Jiro
发明人： FANUC LTD
IPC分类号： G06F15/16
CPC分类号： G06F9/3885 , G06F9/3879
摘要： A processing unit having at least one coprocessor (15, 16), which comprises a host processor (11), a system memory (12), an input/output device, coprocessors (15, 16) and buses (14, 22, 23) for connecting them. The processing unit further comprises code memories (19, 20) for storing instruction codes for the coprocessors (15, 16), a data memory (21) for storing data that will be used by the coprocessors (15, 16), and address generators (17, 18) which enable the coprocessors (15, 16) to access the code memories (19, 20) and the data memory (21). The host processor (11) sets a group of instruction codes to the code memories (19, 20), sets the data for use in the operation to the data memory (21), and gives an execution instruction to the coprocessors (15, 16). The coprocessors (15, 16) are separated from the host processor (11) to execute the operation.

8. 发明申请

WO1993015450A1 GRAPHIC INTERFERENCE CHECK APPARATUS 审中-公开
标题翻译：图形干扰检查装置
公开(公告)号：WO1993015450A1
公开(公告)日：1993-08-05
申请号：PCT/JP1993000098
申请日：1993-01-27
申请人： FANUC, LTD , KINOSHITA, Jiro , HAMADA, Youichi
发明人： FANUC, LTD
IPC分类号： G05B19/405
CPC分类号： G05B19/4069 , G05B2219/35316
摘要： A graphic interference check apparatus for a machining program which eliminates time and labour by merely generating one screen data. In an NC apparatus including a graphic system which includes a host CPU (31), a graphic controller (32), a frame buffer (33), a P/S convertor (34) for converting a parallel signal to a serial signal, a video driving unit (36) and a video apparatus (40), and wherein the host CPU (31), the graphic controller (32) and the frame buffer (33) are connected by a bus line, the check apparatus of the invention comprises a latch circuit (37) for latching image data continuously outputted from the P/S convertor (34) for each pixel and a comparison circuit (38) for comparing two adjacent image data between the output of the P/S convertor (34) and the output of the latch circuit (37) with respect to at least two image data set from the host CPU (31) for checking interference, detecting interference and outputting an interrupt signal to the host CPU (31). The host CPU (31) may be provided with the function of the graphic controller (32).

9. 发明申请

WO1990002981A1 SYSTEM FOR DIAGNOSING CNC 审中-公开
标题翻译：用于诊断CNC的系统
公开(公告)号：WO1990002981A1
公开(公告)日：1990-03-22
申请号：PCT/JP1989000855
申请日：1989-08-22
申请人： FANUC LTD , KINOSHITA, Jiro
发明人： FANUC LTD
IPC分类号： G05B19/405
CPC分类号： G05B19/4063 , G05B2219/33287 , G05B2219/33288 , G05B2219/33327
摘要： A CNC diagnosing system for monitoring the internal conditions of a CNC (numerical controller). Under the ordinary CNC operation mode, a processor (11) of CNC operates as a host processor, and a processor (1) for diagnosis monitors the processor (11) of CNC and other processors (18a, 24). In the diagnosis mode, the processor (1) for diagnosis works as a host processor, and drives a software that diagnoses the CNC processor (11) and other processors (18a, 24), such that abnormal places in the CNC can be found. In case trouble has developed, therefore, the restoration can be effected in short periods of time, and the CNC exhibits improved reliability.
摘要翻译：一种CNC诊断系统，用于监控CNC（数控）的内部状况。在普通CNC操作模式下，CNC的处理器（11）作为主机处理器，并且用于诊断的处理器（1）监视CNC和其他处理器（18a，24）的处理器（11）。在诊断模式中，用于诊断的处理器（1）用作主处理器，并且驱动诊断CNC处理器（11）和其他处理器（18a，24）的软件，使得可以找到CNC中的异常位置。因此，在发生故障的情况下，可以在短时间内进行恢复，并且可靠性提高。

10. 发明申请

WO1989012854A1 OPERATION PROCESSING UNIT 审中-公开
标题翻译：操作处理单元
公开(公告)号：WO1989012854A1
公开(公告)日：1989-12-28
申请号：PCT/JP1989000608
申请日：1989-06-17
申请人： FANUC LTD , KINOSHITA, Jiro
发明人： FANUC LTD
IPC分类号： G05B19/04
CPC分类号： G05B19/052
摘要： An operation processing unit for processing a program that includes a function instruction, a byte logic operation instruction and a bit logic operation instruction. This unit has a control processor (1) for controlling the whole arithmetic unit, a ladder instruction memory (11) for storing a program, a processor (13) for instructing function, a processor (14) for instructing byte logic operation, and a processor (15) for instructing bit logic operation. These processors (13, 14, 15) process the programs in parallel, and the processings are arbitrated by an arbitration circuit (12).

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