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1. 发明申请

WO2009029289A1 METHOD, APPARATUS, AND ARCHITECTURE FOR AUTOMATED INTERACTION BETWEEN SUBSCRIBERS AND ENTITIES 审中-公开
标题翻译：用户和实体之间自动交互的方法，设备和架构
公开(公告)号：WO2009029289A1
公开(公告)日：2009-03-05
申请号：PCT/US2008/053833
申请日：2008-02-13
申请人： SANDBRIDGE TECHNOLOGIES, INC. , PARSON, Dale, E. , GLOSSNER, C., John , JINTURKAR, Sanjay
发明人： PARSON, Dale, E. , GLOSSNER, C., John , JINTURKAR, Sanjay
IPC分类号： G08G1/123
CPC分类号： G06Q10/00
摘要： A method for interaction between a subscriber and an entity includes determining a current locus and acquiring change in status information for a subscriber. Preference information, for one or more searchable parameters selected by the subscriber, and association information, for one ore more contacts made by the subscriber, are acquired. First and second strength information is then acquired. First strength information pertains to the subscriber's affinity for the preference information and second strength information encompasses the subscriber's affinity for the association information. Responsive to the change in status information, a group of first entities is selected. First entity information about the group of first entities is then generated. The current locus information, the preference information, the association information, the first strength information, and the second strength information are correlated with the first entity information to produce correlation information. Finally, the correlation information is provided to the subscriber to be displayed.
摘要翻译：用户和实体之间的交互的方法包括确定当前轨迹并获取用户状态信息的改变。获取用户选择的一个或多个可搜索参数的优先信息以及用户制作的一个或多个联系人的关联信息。然后获取第一和第二强度信息。第一强度信息与用户对偏好信息的亲和性有关，第二强度信息包括用户对关联信息的亲和度。响应状态信息的变化，选择一组第一实体。然后生成关于第一实体组的第一实体信息。将当前轨迹信息，偏好信息，关联信息，第一强度信息和第二强度信息与第一实体信息相关联以产生相关信息。最后，将相关信息提供给要显示的用户。

2. 发明申请

WO2015119886A1 METHOD AND APPARATUS FOR ENABLING A PROCESSOR TO GENERATE PIPELINE CONTROL SIGNALS 审中-公开
标题翻译：使用处理器生成管道控制信号的方法和装置
公开(公告)号：WO2015119886A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/014064
申请日：2015-02-02
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC. , GLOSSNER, C., John , NACER, Gary, J. , SENTHILVELAN, Murugappan , KALASHNIKOV, Vitaly , HOANE, Arthur, J. , D'ARCY, Paul , IANCU, Sabin, D. , WANG, Shenghong
发明人： GLOSSNER, C., John , NACER, Gary, J. , SENTHILVELAN, Murugappan , KALASHNIKOV, Vitaly , HOANE, Arthur, J. , D'ARCY, Paul , IANCU, Sabin, D. , WANG, Shenghong
IPC分类号： H04W72/12
CPC分类号： G06F9/3822 , G06F9/3836 , G06F9/3853
摘要： A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.
摘要翻译：计算机处理器的链接位解码器接收指令流。链接位解码器从指令流中选择一组指令。链接位解码器从指令流的每个指令中提取指定的位以产生一系列链接位。链接位解码器解码链接序列。考虑到解码的链接序列，链接位解码器识别所选择的指令组之中的零个或多个指令流相关性。链接位解码器输出控制信号以使得处理器的一个或多个管线级鉴于所述组指令序列中所识别的零个或多个指令流依赖性来执行所选择的指令组。

3. 发明申请

WO2005046109A3 CONVERGENCE DEVICE WITH DYNAMIC PROGRAM THROTTLING BASED ON POWER INDICATOR 审中-公开
标题翻译：基于功率指示器的动态程序旋转的积分装置
公开(公告)号：WO2005046109A3
公开(公告)日：2006-06-22
申请号：PCT/US2004035216
申请日：2004-10-25
申请人： SANDBRIDGE TECHNOLOGIES INC , WEINBERGER GUENTER , GLOSSNER C JOHN
发明人： WEINBERGER GUENTER , GLOSSNER C JOHN
IPC分类号： G06F1/32 , H04L29/06 , G06F1/26
CPC分类号： G06F1/329 , G06F1/3203 , H04L69/18 , Y02D10/24 , Y02D50/20
摘要： Techniques for conserving power by controlling program execution in a convergence device comprising a battery or other power source and at least one processor. The processor is configured to perform processing operations associated with voice call communication functions and to perform processing operations associated with data communication functions, and is operative to execute critical programs and noncritical programs. The convergence device stores, for at least a given one of a plurality of noncritical programs associated with the data communication functions, an identifier of at least one alternate capacity program capable of performing substantially the same function as the given program but having a different power source capacity associated therewith. Based at least in part on a power indicator representative of remaining capacity or another characteristic of the power source, execution of the given program may be replaced with execution of the alternate capacity program, such that an amount of power source capacity utilizable for the voice call communication functions is increased.
摘要翻译：通过控制包括电池或其他电源的收敛装置中的程序执行来节省功率的技术以及至少一个处理器。处理器被配置为执行与语音呼叫通信功能相关联的处理操作并且执行与数据通信功能相关联的处理操作，并且可操作以执行关键程序和非关键程序。汇聚装置存储与数据通信功能相关联的多个非关键程序中的至少一个给定的一个，能够执行与给定程序基本上相同的功能但具有不同的电源的至少一个备用容量程序的标识符与之相关的容量。至少部分地基于表示剩余容量的功率指示符或电源的另一特性，可以用执行备用容量程序来替换给定程序的执行，使得可用于语音呼叫的电源容量的量通信功能增加。

4. 发明申请

WO2005046109A2 CONVERGENCE DEVICE WITH DYNAMIC PROGRAM THROTTLING BASED ON POWER INDICATOR 审中-公开
标题翻译：基于功率指示器的动态程序旋转的积分装置
公开(公告)号：WO2005046109A2
公开(公告)日：2005-05-19
申请号：PCT/US2004/035216
申请日：2004-10-25
申请人： SANDBRIDGE TECHNOLOGIES, INC. , WEINBERGER, Guenter , GLOSSNER, C., John
发明人： WEINBERGER, Guenter , GLOSSNER, C., John
IPC分类号： H04L
CPC分类号： G06F1/329 , G06F1/3203 , H04L69/18 , Y02D10/24 , Y02D50/20
摘要： Techniques for conserving power by controlling program execution in a convergence device comprising a battery or other power source and at least one processor. The processor is configured to perform processing operations associated with voice call communication functions and to perform processing operations associated with data communication functions, and is operative to execute critical programs and noncritical programs. The convergence device stores, for at least a given one of a plurality of noncritical programs associated with the data communication functions, an identifier of at least one alternate capacity program capable of performing substantially the same function as the given program but having a different power source capacity associated therewith. Based at least in part on a power indicator representative of remaining capacity or another characteristic of the power source, execution of the given program may be replaced with execution of the alternate capacity program, such that an amount of power source capacity utilizable for the voice call communication functions is increased.
摘要翻译：通过控制包括电池或其他电源的收敛装置中的程序执行来节省功率的技术以及至少一个处理器。处理器被配置为执行与语音呼叫通信功能相关联的处理操作并且执行与数据通信功能相关联的处理操作，并且可操作以执行关键程序和非关键程序。汇聚装置存储与数据通信功能相关联的多个非关键程序中的至少一个给定的一个，能够执行与给定程序基本上相同的功能但具有不同的电源的至少一个备用容量程序的标识符与之相关的容量。至少部分地基于表示剩余容量的功率指示符或电源的另一特性，可以用执行备用容量程序来替换给定程序的执行，使得可用于语音呼叫的电源容量的量通信功能增加。

5. 发明申请

WO2006071385A2 DATA FILE STORING MULTIPLE DATA TYPES WITH CONTROLLED DATA ACCESS 审中-公开
标题翻译：数据文件存储具有受控数据访问的多种数据类型
公开(公告)号：WO2006071385A2
公开(公告)日：2006-07-06
申请号：PCT/US2005/041419
申请日：2005-11-15
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C.,John , SCHULTE, Michael, J.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C.,John , SCHULTE, Michael, J.
IPC分类号： G06F15/00
CPC分类号： G06F9/30112
摘要： A method and apparatus for efficiently storing multiple data types in a computer’s register or data file. A single data file can store data with a variety of sizes and number formats, including integers, fractions, and mixed numbers. The register file is partitioned into fields, such that only the relevant portions of the register file are read or written.
摘要翻译：一种用于在计算机的寄存器或数据文件中有效地存储多种数据类型的方法和装置。单个数据文件可以存储具有各种大小和数字格式的数据，包括整数，分数和混合数。寄存器文件被分割成字段，使得仅读取或写入寄存器文件的相关部分。

6. 发明申请

WO2005101221A1 MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD 审中-公开
标题翻译：多通道加工器，每个螺纹多个并流管道
公开(公告)号：WO2005101221A1
公开(公告)日：2005-10-27
申请号：PCT/US2005/011614
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J. , GLOSSNER, C., John
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J. , GLOSSNER, C., John
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/30036 , G06F9/30101 , G06F9/30123 , G06F9/3893
摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.
摘要翻译：多线程处理器包括多个硬件线程单元，耦合到用于解码从其接收的指令的线程单元的指令解码器，以及用于执行解码指令的多个执行单元。多线程处理器被配置为用于控制与相应硬件线程单元相关联的线程的指令发布序列。在给定的处理器时钟周期中，仅允许指定的一个线程发出一个或多个指令，但是允许发出指令的指定线程根据指令发布顺序在多个时钟周期内变化。这些指令以允许至少给定的一个线程支持多个并行指令流水线的方式流水线化。

7. 发明申请

WO2005086675A2 ARITHMETIC CIRCUIT WITH BALANCED LOGIC LEVELS FOR LOW-POWER OPERATION 审中-公开
标题翻译：具有平衡逻辑电平的低功耗操作的算术电路
公开(公告)号：WO2005086675A2
公开(公告)日：2005-09-22
申请号：PCT/US2005/007021
申请日：2005-03-04
申请人： SANDBRIDGE TECHNOLOGIES, INC. , CHIRCA, Kai , GLOSSNER, C., John
发明人： CHIRCA, Kai , GLOSSNER, C., John
IPC分类号： G06F7/50
CPC分类号： G06F7/506
摘要： An adder circuit comprising a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least give one of the adder stages are substantially balanced in terms of a number of gate delays experienced by said signals within said adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.
摘要翻译：一种加法器电路，包括串联互连的多个加法器级，除了最后加法级之外的每个加法级的进位被耦合到后一个加法级的进位。至少给出加法器级中的一个，进位，产生和传播施加到进位计算元件的相应输入端的信号在所述加法器电路中达到其相应输入时所经历的门数延迟的数目基本平衡的进位计算元素。有利地，这提供了加法器电路中的动态开关功率和短路功率的显着降低。

8. 发明申请

WO2006071385A3 DATA FILE STORING MULTIPLE DATA TYPES WITH CONTROLLED DATA ACCESS 审中-公开
标题翻译：数据文件存储具有受控数据访问的多种数据类型
公开(公告)号：WO2006071385A3
公开(公告)日：2009-04-09
申请号：PCT/US2005041419
申请日：2005-11-15
申请人： SANDBRIDGE TECHNOLOGIES INC , HOKENEK ERDEM , MOUDGILL MAYAN , GLOSSNER C JOHN , SCHULTE MICHAEL J
发明人： HOKENEK ERDEM , MOUDGILL MAYAN , GLOSSNER C JOHN , SCHULTE MICHAEL J
IPC分类号： G06F12/04
CPC分类号： G06F9/30112
摘要： A method and apparatus for efficiently storing multiple data types in a computer's register or data file. A single data file can store data with a variety of sizes and number formats, including integers, fractions, and mixed numbers. The register file is partitioned into fields, such that only the relevant portions of the register file are read or written.
摘要翻译：一种用于在计算机的寄存器或数据文件中有效地存储多种数据类型的方法和装置。单个数据文件可以存储具有各种大小和数字格式的数据，包括整数，分数和混合数。寄存器文件被分割成字段，使得仅读取或写入寄存器文件的相关部分。

9. 发明申请

WO2005099383A3 PROCESSOR HAVING COMPOUND INSTRUCTION AND OPERATION FORMATS 审中-公开
标题翻译：具有化合物指导和操作格式的处理器
公开(公告)号：WO2005099383A3
公开(公告)日：2007-07-19
申请号：PCT/US2005011613
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES INC , GLOSSNER C JOHN , HOKENEK ERDEM , MOUDGILL MAYAN , SCHULTE MICHAEL J
发明人： GLOSSNER C JOHN , HOKENEK ERDEM , MOUDGILL MAYAN , SCHULTE MICHAEL J
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30036 , G06F9/30167 , G06F9/3853
摘要： A processor (400) comprises a memory (412-1), an instruction decoder (416) coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units (460) for executing the decoded instructions One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.
摘要翻译：处理器（400）包括存储器（412-1），耦合到存储器的指令解码器（416），用于解码从其中检索的指令;以及多个执行单元（460），用于执行解码指令一个或多个指令处于复合指令格式，其中单个指令包括多个操作字段，其中一个或多个操作字段各自至少包括操作码字段和功能字段。操作代码字段和功能字段一起指定由一个或多个执行单元执行的特定操作。

10. 发明申请

WO2005086675A3 ARITHMETIC CIRCUIT WITH BALANCED LOGIC LEVELS FOR LOW-POWER OPERATION 审中-公开
标题翻译：具有平衡逻辑电平的低功耗操作的算术电路
公开(公告)号：WO2005086675A3
公开(公告)日：2007-07-05
申请号：PCT/US2005007021
申请日：2005-03-04
申请人： SANDBRIDGE TECHNOLOGIES INC , CHIRCA KAI , GLOSSNER C JOHN
发明人： CHIRCA KAI , GLOSSNER C JOHN
IPC分类号： G06F7/50
CPC分类号： G06F7/506
摘要： An adder circuit comprising a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least give one of the adder stages are substantially balanced in terms of a number of gate delays experienced by said signals within said adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.
摘要翻译：一种加法器电路，包括串联互连的多个加法器级，除了最后一个加法器级之外的每个加法器级的进位被耦合到后一个加法级的进位。至少给出加法器级中的一个，进位，产生和传播施加到进位计算元件的相应输入端的信号在所述加法器电路中达到其相应输入时所经历的门数延迟的数目基本平衡的进位计算元素。有利地，这提供了加法器电路中的动态开关功率和短路功率的显着降低。

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