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1. 发明申请

WO2009076281A1 ACCELERATING TRACEBACK ON A SIGNAL PROCESSOR 审中-公开
标题翻译：加速信号处理器的跟踪
公开(公告)号：WO2009076281A1
公开(公告)日：2009-06-18
申请号：PCT/US2008/085842
申请日：2008-12-08
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan , AGRAWAL, Sitij
发明人： MOUDGILL, Mayan , AGRAWAL, Sitij
IPC分类号： G06F15/00
CPC分类号： G06F9/30018 , G06F9/345 , G06F9/355
摘要： A method executed by an instruction set on a processor is described. The method includes providing a tbbit instruction, inputting a first index for the tbbit instruction, loading a second value for the tbbit instruction, wherein the second value comprises at least 2b bits, using selected b bits of the first index to select at least one target bit in the loaded second value, shifting the target bit into the bottom of the first index, and computing a second index based on the shifting of the target bit into the bottom of the first index. Other methods and variations are also described.
摘要翻译：描述由处理器上的指令集执行的方法。该方法包括提供tbbit指令，输入tbbit指令的第一索引，为tbbit指令加载第二值，其中使用所选择的第一索引的b位选择至少一个目标，其中第二值包括至少2b位将目标位移动到第一索引的底部，并且基于目标位移到第一索引的底部来计算第二索引。还描述了其它方法和变型。

2. 发明申请

WO2009067283A2 METHOD FOR IMPLEMENTING PERIODIC BEHAVIORS USING A SINGLE REFERENCE 审中-公开
标题翻译：使用单一参考实现周期性行为的方法
公开(公告)号：WO2009067283A2
公开(公告)日：2009-05-28
申请号：PCT/US2008074646
申请日：2008-08-28
申请人： SANDBRIDGE TECHNOLOGIES INC , MOUDGILL MAYAN
发明人： MOUDGILL MAYAN
IPC分类号： G06F1/14
CPC分类号： G06F9/325
摘要： A method for processing information is described. The method includes providing a phase reference, Fi, where the phase reference comprises N distinct values, expressed as Fi, = F0...FN-1. A reset signal is received. The phase reference, F0, is initialized in response to receipt of the reset signal. The phase reference values are repeatedly advanced from F0 through FN-1. The process then includes enabling at least one function at a predetermined phase reference value FA, wherein F? e {F0...FN-1 }
摘要翻译：描述处理信息的方法。该方法包括提供相位参考Fi，其中相位参考包括N个不同值，表示为Fi，= F0 ... FN-1。接收复位信号。响应于接收到复位信号，初始化相位基准F0。相位参考值从F0到FN-1重复进行。然后，该过程包括在预定相位参考值FA中启用至少一个功能，其中F e {F0 ... FN-1}

3. 发明申请

WO2005013626A2 RAKE RECEIVER WITH MULTI-PATH INTERFERENCE ACCOMMODATION 审中-公开
标题翻译： RAKE接收机具有多路干扰存储
公开(公告)号：WO2005013626A2
公开(公告)日：2005-02-10
申请号：PCT/US2004/023665
申请日：2004-07-26
申请人： SANDBRIDGE TECHNOLOGIES, INC. , IANCU, Daniel , GLOSSNER, John , MOUDGILL, Mayan
发明人： IANCU, Daniel , GLOSSNER, John , MOUDGILL, Mayan
IPC分类号： H04Q
CPC分类号： H04B1/7115 , H04B1/7107 , H04B1/712 , H04L25/0202
摘要： A method of extracting data from a received signal including multi-path interference in a rake receiver. The method includes sampling and filtering the received signal; estimating a time delay (a) between paths for the filtered samples ψ(τ); and estimating channel complex coefficient (b) for the filtered samples ψ(τ). Transmitted data x(τ 1 ) is extracted from the filtered samples ψ(τ) for each path l by solutions of simultaneous equations of the following filtered samples ψ(τ) equation (Formula I) wherein k is a particular path, N p is the number of visible paths, (c) is a a double convolution matrix of the filtering process and (d) is the pseudo inverse, A ss (τ l ) is the product of spreading and scrambling matrices and (e) is the inverse, and (f) is noise.
摘要翻译：一种从包含多径干扰的接收信号中提取数据的方法。该方法包括对接收到的信号进行采样和滤波; 估计滤波样本的路径之间的时间延迟（a）psi（τ）; 并估计滤波样本psi（τ）的信道复数系数（b）。通过以下过滤采样的联立方程式（τ）方程式（式I）的解的解，从每个路径l的滤波样本psi（τ）中提取发射数据x（τ1），其中k是特定路径，N p是数（c）是滤波过程的双卷积矩阵，（d）是伪逆，Ass（taul）是扩频和加扰矩阵的乘积，（e）是逆的，（f）是噪声。

4. 发明申请

WO2018112340A1 IMPLEMENTING ATOMIC PRIMITIVES USING CACHE LINE LOCKING 审中-公开
公开(公告)号：WO2018112340A1
公开(公告)日：2018-06-21
申请号：PCT/US2017/066670
申请日：2017-12-15
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC. , MOUDGILL, Mayan , HOANE, A., Joseph
发明人： MOUDGILL, Mayan , HOANE, A., Joseph
IPC分类号： G06F13/00
摘要： A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.

5. 发明申请

WO2009105332A1 METHOD TO ACCELERATE NULL-TERMINATED STRING OPERATIONS 审中-公开
标题翻译：加速空终止操作的方法
公开(公告)号：WO2009105332A1
公开(公告)日：2009-08-27
申请号：PCT/US2009/032987
申请日：2009-02-03
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan
发明人： MOUDGILL, Mayan
IPC分类号： G06F7/38
CPC分类号： G06F7/02
摘要： A method reads and compares first and second register values, each with a size of at least two bytes. A third register indicates a match if: (1) a byte in the first register value is equal to (or, alternatively, not equal to) a corresponding byte in the second register value, or (2) if a byte in the first register value is zero. Next, a fourth register value is set to one of the following: (1) a count of the matching byte, if the corresponding bytes in the first and second register values are equal (or, alternatively, are not equal), or (2) a number outside of a range between 0 and n - 1, if the corresponding bytes in the first and second register values are not equal (or, alternatively, are equal). The value, n, is an integer equal to the number of bytes in the first and second register values.
摘要翻译：一种方法读取并比较第一和第二寄存器值，每个寄存器值的大小至少为两个字节。第三个寄存器表示匹配：（1）第一个寄存器值中的一个字节等于（或者不等于）第二个寄存器值中相应的字节，或者（2）如果第一个寄存器中的一个字节值为零。接下来，将第四寄存器值设置为以下之一：（1）匹配字节的计数，如果第一和第二寄存器值中的相应字节相等（或者替代地，不相等），或（2 ）如果第一和第二寄存器值中的相应字节不相等（或者可选地，等于），则在0和n-1之间的范围之外的数字。值n是与第一和第二寄存器值中的字节数相等的整数。

6. 发明申请

WO2008070250A9 SOFTWARE IMPLEMENTATION OF MATRIX INVERSION IN A WIRELESS COMMUNICATION SYSTEM 审中-公开
标题翻译：无线通信系统中矩阵反演的软件实现
公开(公告)号：WO2008070250A9
公开(公告)日：2008-09-12
申请号：PCT/US2007079305
申请日：2007-09-24
申请人： SANDBRIDGE TECHNOLOGIES INC , SIMA MIHAI , IANCU DANIEL , YE HUA , MOUDGILL MAYAN
发明人： SIMA MIHAI , IANCU DANIEL , YE HUA , MOUDGILL MAYAN
IPC分类号： G06F15/00
CPC分类号： G06F17/16 , G06F9/30014 , G06F9/30036 , G06F9/30101 , G06F9/3851 , G06F9/3867 , G06F9/3885 , G06F9/3895
摘要： A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.
摘要翻译：数字信号处理器被提供在无线通信设备中，其中处理器包括矢量单元，耦合到矢量单元并且可由矢量单元访问的第一和第二寄存器; 以及指令集，被配置为使用矢量单元以及第一寄存器和第二寄存器，通过坐标旋转数字计算机指令来执行信道值矩阵的矩阵求逆。

7. 发明申请

WO2005013626A3 RAKE RECEIVER WITH MULTI-PATH INTERFERENCE ACCOMMODATION 审中-公开
标题翻译：具有多路干扰的RAKE接收机
公开(公告)号：WO2005013626A3
公开(公告)日：2005-05-12
申请号：PCT/US2004023665
申请日：2004-07-26
申请人： SANDBRIDGE TECHNOLOGIES INC , IANCU DANIEL , GLOSSNER JOHN , MOUDGILL MAYAN
发明人： IANCU DANIEL , GLOSSNER JOHN , MOUDGILL MAYAN
IPC分类号： H04B1/707 , H04L25/02 , H04Q20060101
CPC分类号： H04B1/7115 , H04B1/7107 , H04B1/712 , H04L25/0202
摘要： A method of extracting data from a received signal including multi-path interference in a rake receiver. The method includes sampling and filtering the received signal; estimating a time delay (a) between paths for the filtered samples psi(tau); and estimating channel complex coefficient (b) for the filtered samples psi(tau). Transmitted data x(tau1) is extracted from the filtered samples psi(tau) for each path l by solutions of simultaneous equations of the following filtered samples psi(tau) equation (Formula I) wherein k is a particular path, Np is the number of visible paths, (c) is a a double convolution matrix of the filtering process and (d) is the pseudo inverse, Ass (taul) is the product of spreading and scrambling matrices and (e) is the inverse, and (f) is noise.
摘要翻译：在瑞克接收机中从包括多径干扰的接收信号中提取数据的方法。该方法包括对接收到的信号进行采样和滤波; 估计滤波样本的路径之间的时间延迟（α）psi（tau）; 并估计滤波样本psi（τ）的信道复数系数（b）。通过以下滤波样本的联立方程式的解，从每个路径l的滤波样本psi（tau）中提取传输数据x（tau1）psi（tau）等式（公式I）其中k是特定路径，Np是数字（c）是滤波过程的双重卷积矩阵，（d）是伪逆，（（taul）是扩展矩阵和加扰矩阵的乘积，（e）是逆矩阵，（f）是噪声。

8. 发明申请

WO2010025074A1 LATCH-BASED IMPLEMENTATION OF A REGISTER FILE FOR A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：用于多线程处理器的寄存器文件的基于锁存器的实现
公开(公告)号：WO2010025074A1
公开(公告)日：2010-03-04
申请号：PCT/US2009/054421
申请日：2009-08-20
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan , NACER, Gary , WANG, Shenghong
发明人： MOUDGILL, Mayan , NACER, Gary , WANG, Shenghong
IPC分类号： G06F15/76
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123
摘要： A processor register file for a multi-threaded processor is described. The processore register file includes, in one embodiment, T threads, having N b-bit wide registers. Each of the registers includes a b-bit master latch, T b-bit slave latches connected to the master latch, and a slave latch write enable connected to the slave latches. The master latch is not opened at the same time as the slave latches. In addition, only one of the slave latches is enabled at any given time. As should be apparent to those skilled in the art, T, N, and b are all integers. Other embodiments and variations are also provided.
摘要翻译：描述用于多线程处理器的处理器寄存器文件。在一个实施例中，处理器寄存器文件包括具有N个b位宽寄存器的T线程。每个寄存器包括一个b位主锁存器，连接到主锁存器的T b位从属锁存器和一个从锁存器写使能，连接到从锁存器。主锁存器不会与从动锁存器同时打开。此外，在任何给定时间只有一个从锁存器被使能。对于本领域技术人员来说显而易见的是，T，N和b都是整数。还提供了其他实施例和变型。

9. 发明申请

WO2009140142A1 IMPLEMENTATION OF ARBITRARY GALOIS FIELD ARITHMETIC ON A PROGRAMMABLE PROCESSOR 审中-公开
标题翻译：对可编程处理器进行仲裁GALOIS场算法的实现
公开(公告)号：WO2009140142A1
公开(公告)日：2009-11-19
申请号：PCT/US2009/043179
申请日：2009-05-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan
发明人： MOUDGILL, Mayan
IPC分类号： G06F7/00
CPC分类号： G06F7/724 , G06F7/722 , G06F9/3001
摘要： A method for a Galois Field multiply includes executing first and second instructions. The first inctruction includes receiving a first input, such as a first variable, receiving a second input, such as a second variable, performing a polynomial multiplication over GF(2 m ), using the first and second inputs, and producing a product. The second instruction includes receiving a third input, which may be the product from the first instruction, receiving a fourth input, which is a predetermined generator polynomial to operate upon the product, receiving a fifth input, which is a length of the predetermined generator polynomial, to limit operation of the predetermined generator polynomial upon the product, and computing, via the predetermined generator polynomial limited by the length, a modulus of the product with respect to a divisor. A hardware block is also described.
摘要翻译： Galois域乘法的方法包括执行第一和第二指令。第一种形式包括：使用第一和第二输入接收诸如第一变量的第一输入，接收诸如第二变量的第二输入，使用GF（2m）执行多项式乘法，并产生乘积。第二指令包括接收第三输入，其可以是来自第一指令的乘积，接收作为对产品进行操作的预定生成多项式的第四输入，接收作为预定生成多项式的长度的第五输入，以限制产品上的预定生成多项式的运算，并且经由长度限制的预定生成多项式计算乘积相对于除数的模数。还描述了硬件块。

10. 发明申请

WO2008060948A3 METHOD AND SYSTEM FOR PARALLELIZATION OF PIPELINED COMPUTATIONS 审中-公开
标题翻译：用于并行计算的并行化方法和系统
公开(公告)号：WO2008060948A3
公开(公告)日：2008-07-24
申请号：PCT/US2007084113
申请日：2007-11-08
申请人： SANDBRIDGE TECHNOLOGIES INC , KOTLYAR VLADIMIR , MOUDGILL MAYAN , POGUDIN YURIY M
发明人： KOTLYAR VLADIMIR , MOUDGILL MAYAN , POGUDIN YURIY M
IPC分类号： G06F15/00
CPC分类号： G06F9/5066 , G06F9/3826 , G06F9/3885 , G06F9/5027
摘要： A method of parallelizing a pipeline includes stages operable on a sequence of work items. The method includes allocating an amount of work for each work item, assigning at least one stage to each work item, partitioning the at least one stage into at least one team, partitioning the at least one team into at least one gang, and assigning the at least one team and the at least one gang to at least one processor. Processors, gangs, and teams are juxtaposed near one another to minimize communication losses.
摘要翻译：流水线并行化的方法包括可在一系列工作项上操作的阶段。该方法包括为每个工作项分配一定量的工作，为每个工作项分配至少一个阶段，将至少一个阶段划分成至少一个团队，将至少一个团队划分成至少一个团队，以及分配至少一个团队和至少一个团伙到至少一个处理器。处理器，帮派和团队彼此并列，以最大限度减少通信损失。

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