专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006006076A8 LOW-POWER RECONFIGURABLE ARCHITECTURE FOR SIMULTANEOUS IMPLEMENTATION OF DISTINCT COMMUNICATION STANDARDS 审中-公开
标题翻译：低功耗可重构结构同步实现异步通信标准
公开(公告)号：WO2006006076A8
公开(公告)日：2007-01-04
申请号：PCT/IB2005002485
申请日：2005-05-18
申请人： ASOCS LTD , GARON GILAD
发明人： GARON GILAD , SOLOMON DORON
IPC分类号： G06F13/42
CPC分类号： G06F9/44505 , G06F13/4022 , G06F15/7867 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.
摘要翻译：公开了一种用于处理根据由一系列算法定义的多个通信协议中的任何一个编码的信号的芯片架构。芯片架构包括多个宏功能，每个巨型功能以可重用的可重新配置功能块的形式，用于实现实现每个通信协议的物理层所必需的不同算法; 以及多个开关，被配置为响应选择的控制信号，以便互连所需的宏功能，以处理用每个协议编码的信号。优选地，使用两个或多个协议的算法来使用至少一些相同的宏功能。

2. 发明申请

WO2006014528A1 A METHOD OF AND APPARATUS FOR IMPLEMENTING FAST ORTHOGONAL TRANSFORMS OF VARIABLE SIZE 审中-公开
标题翻译：用于实现可变尺寸的快速正交变换的方法和装置
公开(公告)号：WO2006014528A1
公开(公告)日：2006-02-09
申请号：PCT/US2005/024063
申请日：2005-07-08
申请人： ASOCS LTD. , SOLOMON, Doron , GARON, Gilad
发明人： SOLOMON, Doron , GARON, Gilad
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture including: a computational unit (182) configured and arranged so as to include one or more butterfly units; a block including one or more multipliers (184) coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit (180) configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture (180).
摘要翻译：一种用于执行多级矢量快速正交变换的可重构体系结构，其中矢量的大小为N，其中N可以变化，并且级数是N的函数，该架构包括：计算单元（182 ）配置和布置为包括一个或多个蝴蝶单元; 包括耦合到所述计算单元的输出的一个或多个乘法器（184）的块，被配置和布置为对所述变换的至少一个阶段执行所有蝴蝶计算; 存储单元（180），其被配置和布置为存储所述蝶形计算的中间结果和所述计算单元用于执行每个蝶形运算的预定系数，所述存储单元包括存储器和复用架构（180）。

3. 发明申请

WO2006026334A1 A METHOD OF AND APPARATUS FOR IMPLEMENTING A RECONFIGURABLE TRELLIS-TYPE DECODING 审中-公开
标题翻译：一种实现可重构的TRELLIS-TYPE解码的方法和装置
公开(公告)号：WO2006026334A1
公开(公告)日：2006-03-09
申请号：PCT/US2005/030200
申请日：2005-08-24
申请人： ASOCS, LTD. , GARON, Gilad
发明人： GARON, Gilad , SOLOMON, Doron
IPC分类号： H03M13/00
CPC分类号： H03M13/4169 , G06F17/142 , H03M13/1105 , H03M13/2957 , H03M13/39 , H03M13/3966 , H03M13/41 , H03M13/4107 , H03M13/4146 , H03M13/6508 , H03M13/6511 , H03M13/6513 , H03M13/6516 , H03M13/6561
摘要： A chip architectural core is described for use in decoding one or more vectors received by the core in accordance with one or more recursive and/or non-recursive systematic trellis codes of varying sizes and constraints K, as well as generator polynomials. The core comprises: a decoder including (a) a reconfigurable network of ACS blocks (114), BMU generators (110) and trace-back mechanisms (116) for both recursive and non-recursive systematic forms, and (b) reconfigurable connections between the ACS blocks, BMU generators and trace-back mechanisms, arranged so that the precise number of network components can be continuously rearranged and interconnected in a network as a function of size and the constraint K and generator polynomial of each code used for encoding the vectors received by the core.
摘要翻译：描述了芯片架构核心，用于根据一个或多个不同大小和约束K的递归和/或非递归系统网格码以及生成多项式对由核接收的一个或多个向量进行解码。核心包括：解码器，包括（a）用于递归和非递归系统形式的ACS块（114），BMU发生器（110）和跟踪返回机制（116）的可重新配置网络，以及（b） ACS块，BMU发生器和追溯机制被布置成使得网络组件的精确数量可以在网络中作为大小和用于编码矢量的每个代码的约束K和生成多项式的函数被连续地重新排列和互连被核心收到。

4. 发明申请

WO2006006076A2 LOW-POWER RECONFIGURABLE ARCHITECTURE FOR SIMULTANEOUS IMPLEMENTATION OF DISTINCT COMMUNICATION STANDARDS 审中-公开
标题翻译：低功耗可重构结构同步实现异步通信标准
公开(公告)号：WO2006006076A2
公开(公告)日：2006-01-19
申请号：PCT/IB2005/002485
申请日：2005-05-18
申请人： ASOCS LTD. , GARON, Gilad
发明人： SOLOMON, Doron
IPC分类号： G06F13/42
CPC分类号： G06F9/44505 , G06F13/4022 , G06F15/7867 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.
摘要翻译：公开了一种用于处理根据由一系列算法定义的多个通信协议中的任何一个编码的信号的芯片架构。芯片架构包括多个宏功能，每个巨型功能以可重用的可重新配置功能块的形式，用于实现实现每个通信协议的物理层所必需的不同算法; 以及多个开关，被配置为响应选择的控制信号，以便互连所需的宏功能，以处理用每个协议编码的信号。优选地，使用两个或多个协议的算法来使用至少一些相同的宏功能。

5. 发明申请

WO2006006076A3 LOW-POWER RECONFIGURABLE ARCHITECTURE FOR SIMULTANEOUS IMPLEMENTATION OF DISTINCT COMMUNICATION STANDARDS 审中-公开
标题翻译：用于同时实施不同通信标准的低功率可重构架构
公开(公告)号：WO2006006076A3
公开(公告)日：2006-06-01
申请号：PCT/IB2005002485
申请日：2005-05-18
申请人： ASOCS LTD , GARON GILAD
发明人： SOLOMON DORON
IPC分类号： G06F13/42
CPC分类号： G06F9/44505 , G06F13/4022 , G06F15/7867 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.
摘要翻译：公开了一种用于处理根据由一系列算法定义的多个通信协议中的任何一个通信协议编码的信号的芯片架构。该芯片架构包括多个宏功能单元，每个宏功能单元都以可重用的，可重新配置的功能块的形式用于实现实现每个通信协议的物理层所必需的不同算法; 以及多个开关，其被配置为响应于选择控制信号以互连用于处理用每个协议编码的信号的必要宏功能单元。优选地，至少一些相同的宏功能被与两种或更多种协议的算法一起使用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式