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1. 发明申请

WO2013026034A8 ADAPTIVE ULTRA-LOW VOLTAGE MEMORY 审中-公开
标题翻译：自适应超低电压存储器
公开(公告)号：WO2013026034A8
公开(公告)日：2013-06-06
申请号：PCT/US2012051453
申请日：2012-08-17
申请人： BROADCOM CORP , PENZES PAUL , FULLERTON MARK , HUKKOO AJAT , WALLEY JOHN
发明人： PENZES PAUL , FULLERTON MARK , HUKKOO AJAT , WALLEY JOHN
IPC分类号： G06F1/32 , G06F11/10 , G06F12/08
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3296 , G06F11/1064 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , H03M13/19 , H03M13/3715 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).
摘要翻译：实施例提供允许低电压操作模式的自适应存储器。在低电压工作模式下，提供给存储器的电源电压降低到低于Vcc（min），这样可以显着节省最小电压由Vcc（min）决定的电路组件（例如CPU）的功耗）。根据另外的实施例，可以根据期望的功率节省（例如，目标Vcc（min））和/或性能要求（例如，可靠性，高速缓存大小要求等）根据各种配置来动态地配置存储器。

2. 发明申请

WO2013026039A2 PROACTIVE POWER MANAGEMENT USING A POWER MANAGEMENT UNIT 审中-公开
标题翻译：使用电源管理单元实现电源管理
公开(公告)号：WO2013026039A2
公开(公告)日：2013-02-21
申请号：PCT/US2012/051477
申请日：2012-08-17
申请人： BROADCOM CORPORATION , FULLERTON, Mark , WALLEY, John , JUNG, Hwisung
发明人： FULLERTON, Mark , WALLEY, John , JUNG, Hwisung
IPC分类号： G06F1/26 , G06F9/00 , G06F1/32
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Embodiments of the present disclosure provide systems and methods for proactively managing power in a device. A power management unit (PMU) receives information from various subsystems of a device and estimates the total power required by each subsystem of the device. Based on this information, the PMU can predict power requirements for a particular subsystem or for one or more application(s) to execute. Based on this prediction, the PMU can reconfigure the subsystems so that the device executes more efficiently given the current battery life of the device. Proactive power management advantageously gives the PMU the capability to predict power needs of various subsystems of a device so that the power supplied to these subsystems can be managed in an intelligent way before battery resources are exhausted.
摘要翻译：本公开的实施例提供用于主动管理设备中的功率的系统和方法。功率管理单元（PMU）从设备的各个子系统接收信息，并估计设备每个子系统所需的总功率。基于该信息，PMU可以预测特定子系统或一个或多个应用执行的功率需求。基于这一预测，PMU可以重新配置子系统，以便在设备的当前电池寿命时，设备执行得更有效。主动功率管理有利地使PMU能够预测设备的各个子系统的功率需求，使得在电池资源耗尽之前，提供给这些子系统的功率可以以智能的方式进行管理。

3. 发明申请

WO2008100414A1 SECURITY FOR CODES RUNNING IN NON-TRUSTED DOMAINS IN A PROCESSOR CORE 审中-公开
标题翻译：处理器核心中的无信任域名运行代码的安全性
公开(公告)号：WO2008100414A1
公开(公告)日：2008-08-21
申请号：PCT/US2008/001668
申请日：2008-02-08
申请人： MARVELL WORLD TRADE LTD. , FULLERTON, Mark N.
发明人： FULLERTON, Mark N.
IPC分类号： G06F21/00
CPC分类号： H04L63/10 , G06F21/53 , G06F21/54 , G06F21/74
摘要： A method and apparatus configure a trusted domain and a plurality of isolated domains in a processor core. Each isolated domain is assigned a unique domain identifier. One or more resources are associated with each isolated domain. The associations are stored as permissions to access physical addresses of resources. Code to be executed by a hardware device is assigned to one of the isolated domains. The domain identifier for the assigned isolated domain is written to the hardware device. When the hardware device executes the code, each instruction is logically tagged with the domain identifier written to the hardware device. An instruction includes request to access a physical address. The hardware device compares the domain identifier of the instruction with the permissions. If the permissions allow the domain identifier to access the physical address, then access to the resource at the physical address is allowed. Access is otherwise blocked.
摘要翻译：一种方法和设备在处理器核心中配置可信域和多个隔离域。每个隔离域都分配一个唯一的域标识符。一个或多个资源与每个隔离域相关联。关联存储为访问资源物理地址的权限。由硬件设备执行的代码被分配给其中一个隔离域。分配的隔离域的域标识符被写入硬件设备。当硬件设备执行代码时，每条指令都会被写入硬件设备的域标识符进行逻辑标记。指令包括访问物理地址的请求。硬件设备将指令的域标识符与权限进行比较。如果权限允许域标识符访问物理地址，则允许访问物理地址处的资源。访问被阻止。

4. 发明申请

WO2008068612A1 SYSTEM AND METHOD FOR PERIPHERAL DEVICE COMMUNICATIONS 审中-公开
标题翻译：用于外围设备通信的系统和方法
公开(公告)号：WO2008068612A1
公开(公告)日：2008-06-12
申请号：PCT/IB2007/003849
申请日：2007-12-10
申请人： MARVELL WORLD TRADE LTD. , BAR-SHALOM, Ofer , FULLERTON, Mark N. , TSAFRIR, Alon
发明人： BAR-SHALOM, Ofer , FULLERTON, Mark N. , TSAFRIR, Alon
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.
摘要翻译：主机设备包括外围控制模块，其包括从第一存储器接收数据的第一存储器寄存器和与第一存储器通信的直接存储器访问（DMA）模块。主机设备还包括从第一存储器接收数据的主机控制模块。主机设备还包括与第一存储器寄存器，主机控制模块和包括第一存储器阵列的第二存储器通信的DMA控制模块。 DMA控制模块将第一存储器阵列的内容与存储器寄存器的内容进行比较，并且基于比较控制从第一存储器到外围控制模块的数据传输。

5. 发明申请

WO2009140631A3 DISTRIBUTED COMPUTING SYSTEM WITH UNIVERSAL ADDRESS SYSTEM AND METHOD 审中-公开
标题翻译：具有通用地址系统和方法的分布式计算系统
公开(公告)号：WO2009140631A3
公开(公告)日：2010-01-07
申请号：PCT/US2009044200
申请日：2009-05-15
申请人： SMOOTH STONE INC , FULLERTON MARK , EVANS BARRY
发明人： FULLERTON MARK , EVANS BARRY
IPC分类号： G06F13/00
CPC分类号： G06F12/1081 , G06F12/1036
摘要： A distributed computing system that incorporates enhanced distributed storage and a universal address system and method are provided. The system and method are particularly applicable to a server on a chip processing unit. The universal address system and method has greater utility, such as to other computer systems and architectures that can utilize the universal address system and method. The universal address system and method can be used with various processing unit based systems such as single processor systems.
摘要翻译：提供了一种结合增强分布式存储和通用地址系统和方法的分布式计算系统。该系统和方法特别适用于芯片处理单元上的服务器。通用地址系统和方法具有更大的实用性，例如可以利用通用地址系统和方法的其他计算机系统和架构。通用地址系统和方法可以与诸如单处理器系统的各种基于处理单元的系统一起使用。

6. 发明申请

WO2009029643A2 DYNAMIC CORE SWITCHING 审中-公开
标题翻译：动态核心切换
公开(公告)号：WO2009029643A2
公开(公告)日：2009-03-05
申请号：PCT/US2008/074416
申请日：2008-08-27
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Sehat , CHEN, Hong-yi , SAKARDA, Premanand , FULLERTON, Mark N. , HEEB, Jay
发明人： SUTARDJA, Sehat , CHEN, Hong-yi , SAKARDA, Premanand , FULLERTON, Mark N. , HEEB, Jay
IPC分类号： G06F9/46
CPC分类号： G06F1/3293 , G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/38 , G06F9/3885 , G06F9/461 , G06F9/4856 , G06F9/4893 , Y02D10/122 , Y02D10/171 , Y02D10/24 , Y02D10/32 , Y02D50/20
摘要： A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.
摘要翻译：系统包括第一不对称核心，第二不对称核心和核心切换模块。当系统以第一模式操作时，第一不对称核心执行应用程序，而当系统以第二模式操作时，第一不对称核心不活动。当系统以第二模式操作时，第二不对称核心执行应用程序。核心切换模块在第一模式和第二模式之间切换系统的操作。核心切换模块在接收到第一控制信号后，选择性地停止第一不对称核心对应用程序的处理。核心切换模块将第一不对称核心的第一状态传送到第二不对称核心。第二个不对称核心以第二种模式继续执行应用程序。

7. 发明申请

WO2013026039A3 PROACTIVE POWER MANAGEMENT USING A POWER MANAGEMENT UNIT 审中-公开
标题翻译：使用电源管理单元进行功率管理
公开(公告)号：WO2013026039A3
公开(公告)日：2014-05-08
申请号：PCT/US2012051477
申请日：2012-08-17
申请人： BROADCOM CORP , FULLERTON MARK , WALLEY JOHN , JUNG HWISUNG
发明人： FULLERTON MARK , WALLEY JOHN , JUNG HWISUNG
IPC分类号： G05D3/12
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Embodiments of the present disclosure provide systems and methods for proactively managing power in a device. A power management unit (PMU) receives information from various subsystems of a device and estimates the total power required by each subsystem of the device. Based on this information, the PMU can predict power requirements for a particular subsystem or for one or more application(s) to execute. Based on this prediction, the PMU can reconfigure the subsystems so that the device executes more efficiently given the current battery life of the device. Proactive power management advantageously gives the PMU the capability to predict power needs of various subsystems of a device so that the power supplied to these subsystems can be managed in an intelligent way before battery resources are exhausted.
摘要翻译：本公开的实施例提供用于主动管理设备中的功率的系统和方法。电力管理单元（PMU）从设备的各个子系统接收信息，并估计设备每个子系统所需的总功率。基于该信息，PMU可以预测特定子系统或一个或多个应用执行的功率需求。基于这一预测，PMU可以重新配置子系统，以便在设备的当前电池寿命时，设备执行得更有效。主动功率管理有利地使PMU能够预测设备的各个子系统的功率需求，使得在电池资源耗尽之前，能够以智能的方式管理提供给这些子系统的电力。

8. 发明申请

WO2013026034A1 ADAPTIVE ULTRA-LAW VOLTAGE MEMORY 审中-公开
标题翻译：自适应超声波电压存储器
公开(公告)号：WO2013026034A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/051453
申请日：2012-08-17
申请人： BROADCOM CORPORATION , PENZES, Paul , FULLERTON, Mark , HUKKOO, Ajat , WALLEY, John
发明人： PENZES, Paul , FULLERTON, Mark , HUKKOO, Ajat , WALLEY, John
IPC分类号： G06F1/32 , G06F12/08 , G06F11/10
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3296 , G06F11/1064 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , H03M13/19 , H03M13/3715 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).
摘要翻译：实施例提供允许低电压操作模式的自适应存储器。在低电压工作模式下，提供给存储器的电源电压降低到低于Vcc（min），这样可以显着节省最小电压由Vcc（min）决定的电路组件（例如CPU）的功耗）。根据另外的实施例，可以根据期望的功率节省（例如，目标Vcc（min））和/或性能要求（例如，可靠性，高速缓存大小要求等）根据各种配置来动态地配置存储器。

9. 发明申请

WO2009029643A3 DYNAMIC CORE SWITCHING 审中-公开
标题翻译：动态芯切换
公开(公告)号：WO2009029643A3
公开(公告)日：2009-12-30
申请号：PCT/US2008074416
申请日：2008-08-27
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , CHEN HONG-YI , SAKARDA PREMANAND , FULLERTON MARK N , HEEB JAY
发明人： SUTARDJA SEHAT , CHEN HONG-YI , SAKARDA PREMANAND , FULLERTON MARK N , HEEB JAY
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/38 , G06F9/3885 , G06F9/461 , G06F9/4856 , G06F9/4893 , Y02B60/121 , Y02B60/1282 , Y02B60/144 , Y02B60/162 , Y02B60/32 , Y02D10/122 , Y02D10/171 , Y02D10/24 , Y02D10/32 , Y02D50/20
摘要： A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.
摘要翻译：系统包括第一不对称核心，第二非对称核心和核心交换模块。当系统以第一模式操作时，第一非对称核执行应用，并且当系统以第二模式操作时，该状态不活动。当系统以第二模式运行时，第二个非对称核心执行应用程序。核心交换模块在第一模式和第二模式之间切换系统的操作。核心交换模块在接收到第一控制信号之后选择性地停止第一非对称核心处理应用程序。核心交换模块将第一不对称核心的第一状态传送到第二不对称核心。第二非对称核心在第二模式中恢复执行应用程序。

10. 发明申请

WO2006065694A3 PROGRAMMABLE TRANSACTION INITIATOR ARCHITECTURE FOR SYSTEMS WITH SECURE AND NON-SECURE MODES 审中-公开
公开(公告)号：WO2006065694A3
公开(公告)日：2006-06-22
申请号：PCT/US2005/044777
申请日：2005-12-09
申请人： INTEL CORPORATION , OCONNOR, Dennis , FULLERTON, Mark
发明人： OCONNOR, Dennis , FULLERTON, Mark
IPC分类号： G06F13/28 , G06F21/00
摘要： A wireless device dynamically programs a control register for a command-chain driven DMA device. The control register stores a beginning address of the linked list of commands and a secure bit. The secure bit is set if the transaction writing register is secure and a bit in the data being written into the register is set. DMA devices and other bus-mastering peripherals perform tasks described via a command chain that has access to secure resources when the processor is operating in the secure mode and the secure bit is set.

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