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1. 发明申请

WO2007144777A3 INSPECTION SYSTEM EMPLOYING ILLUMINATION THAT IS SELECTABLE OVER A CONTINUOUS RANGE ANGLES 审中-公开
标题翻译：采用连续角度选择的照明系统的检查系统
公开(公告)号：WO2007144777A3
公开(公告)日：2013-07-11
申请号：PCT/IB2007002845
申请日：2007-03-20
申请人： ORBOTECH LTD , HURVITZ TALI , MIZRAHI YARIV DROR , FISCH DAVID
发明人： HURVITZ TALI , MIZRAHI YARIV DROR , FISCH DAVID
IPC分类号： G01N21/00
CPC分类号： G01N21/00 , G01N21/8806 , G01N2021/8825 , G01N2021/9513
摘要： An illumination device and method for inspecting objects having microscopic features is provided. The device includes an illuminator which provides a solid angle of angularly specific illumination defining an illumination angle, selected by a user from among a continuous range of possible illumination angles. The device further includes an object inspector which inspects the object illuminated by the illuminator. The illuminator may include an illumination source, a light concentrator, an illumination angle selector, disposed along a light path between the illumination source and the object inspector. The illumination angle selector may have a first position in which directly -reflected light propagates toward the object plane and a second position in which no light both selected by the illumination angle selector and directly reflected from the object plane enters the collecting lens. Rather, in the second position, only scattered light from the object plane enters the collecting lens.
摘要翻译：提供一种用于检查具有微观特征的物体的照明装置和方法。该装置包括照明器，其提供角度特定照明的立体角，其限定由用户从可能的照射角度的连续范围中选择的照明角度。该装置还包括检查由照明器照亮的物体的物体检查器。照明器可以包括沿着照明源和物体检查器之间的光路布置的照明源，聚光器，照明角度选择器。照明角度选择器可以具有第一位置，其中直接反射的光向物体平面传播，并且第二位置，其中由照明角度选择器选择并且直接从物体平面反射的光不会进入聚光透镜。相反，在第二位置，仅来自物平面的散射光进入收集透镜。

2. 发明申请

WO2007080568A3 SYSTEM AND METHOD FOR INSPECTING WORKPIECES HAVING MICROSCOPIC FEATURES 审中-公开
标题翻译：用于检查具有微观特征的工件的系统和方法
公开(公告)号：WO2007080568A3
公开(公告)日：2009-04-23
申请号：PCT/IL2006001418
申请日：2006-12-11
申请人： ORBOTECH LTD , SAPHIER OFER , ADIN RAANAN , FISCH DAVID
发明人： SAPHIER OFER , ADIN RAANAN , FISCH DAVID
IPC分类号： G06K9/00
CPC分类号： G06K9/033 , G06K2209/19
摘要： Apparatus for high resolution processing of a generally planar workpiece having microscopic features to be imaged, comprising a video camera acquiring at least two candidate images of a microscopic portion on generally planar workpiece; a motion controller operative to effect motion, relative to the workpiece, of at least an optical element of the video camera along an optical axis extending generally normally to a location on a surface of the workpiece, the video camera acquiring the at least two candidate images at selected time intervals, each of the at least two candidate images differing by at least one image parameter; an image selector operative to select an individual image from among the at least two candidate images according to predefined criteria of image quality; and a selected image analyzer operative to analyze at least a portion of the individual image selected by the image selector.
摘要翻译：一种用于具有要成像的微观特征的大体平面的工件的高分辨率处理的装置，包括摄像机，其在大致平面的工件上获取微观部分的至少两个候选图像; 运动控制器，其操作以沿着通常大致延伸到工件表面上的位置的光轴实现至少摄像机的光学元件相对于工件的运动，摄像机获取至少两个候选图像在选定的时间间隔，所述至少两个候选图像中的每一个与至少一个图像参数不同; 图像选择器，用于根据图像质量的预定标准从所述至少两个候选图像中选择单个图像; 以及选择的图像分析器，用于分析由图像选择器选择的单个图像的至少一部分。

3. 发明申请

WO2008085701A2 METHOD AND APPARATUS FOR VARIABLE MEMORY CELL REFRESH 审中-公开
标题翻译：用于可变存储器单元刷新的方法和装置
公开(公告)号：WO2008085701A2
公开(公告)日：2008-07-17
申请号：PCT/US2007/088529
申请日：2007-12-21
申请人： INNOVATIVE SILICON S.A. , FISCH, David , CARMAN, Eric
发明人： FISCH, David , CARMAN, Eric
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2207/104 , G11C2211/4016 , G11C2211/4067
摘要： The embodiments described herein allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. One embodiment includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or more memory cells of a memory array. The circuit integrates a refresh timer element with an event signal generator such that a refresh interval as defined by the refresh timer element is changed when events are detected that may change the data retention time of one or more memory cells. In various embodiments, one or more of the circuits is placed to monitor an entire memory array, different sub-arrays, or different portions of different sub-arrays. This allows additional refresh operations to be closely tied to actual events, thus increasing overall efficiency.
摘要翻译：这里描述的实施例允许使用存储器阵列或存储器本身的系统更有效地控制刷新间隔。这减少了备用电流和与刷新操作相关的开销。一个实施例包括可变模拟刷新信号产生电路，其启动对存储器阵列的一个或多个存储器单元的刷新操作。电路将刷新定时器元件与事件信号发生器集成，使得当检测到可能改变一个或多个存储器单元的数据保持时间的事件时，刷新定时器元件定义的刷新间隔被改变。在各种实施例中，放置一个或多个电路以监视整个存储器阵列，不同子阵列或不同子阵列的不同部分。这允许额外的刷新操作与实际事件紧密相关，从而提高整体效率。

4. 发明申请

WO2005029178A8 A SYSTEM AND METHOD FOR THE DIRECT IMAGING OF COLOR FILTERS 审中-公开
标题翻译：用于彩色滤光片直接成像的系统和方法
公开(公告)号：WO2005029178A8
公开(公告)日：2006-04-13
申请号：PCT/IL2004000882
申请日：2004-09-22
申请人： ORBOTECH LTD , GROSS ABRAHAM , ADIN RAANAN , KATZIR YIGAL , FISCH DAVID
发明人： GROSS ABRAHAM , ADIN RAANAN , KATZIR YIGAL , FISCH DAVID
IPC分类号： G03F20060101 , G03F7/00 , G03F7/20 , G03F
CPC分类号： G03F7/70425 , G03F7/0007 , G03F7/70383
摘要： A system and method for the laser direct imaging of stripe patterns onto a photosensitized surface comprising scanning a laser beam over a photo sensitized, surface. Stripe patterns are exposed by employing a pulse laser and synchronizing the delivery of pulses to expose additive regions of stripes. Alternatively, a laser is scanned over a rotated panel, and the speed of translation, speed of scanning and degree of rotation are coordinated to expose each stripe continuously, and avoid exposing regions between stripes.
摘要翻译：一种用于将条纹图案激光直接成像到光敏表面上的系统和方法，包括在光致敏表面上扫描激光束。通过采用脉冲激光和同步脉冲的传递以暴露条纹的附加区域来暴露条纹图案。或者，激光在旋转的面板上扫描，并且平移速度，扫描速度和旋转程度被协调以连续地暴露每个条纹，并且避免在条纹之间暴露区域。

5. 发明申请

WO2013062612A1 NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIVE COUPLING 审中-公开
标题翻译：具有垂直排水口的非易失性存储器件能够接合电容耦合
公开(公告)号：WO2013062612A1
公开(公告)日：2013-05-02
申请号：PCT/US2012/000528
申请日：2012-10-29
申请人： INVENSAS CORPORATION , FISCH, David, Edward , PARRIS, Michael, Curtis
发明人： FISCH, David, Edward , PARRIS, Michael, Curtis
IPC分类号： H01L21/28 , H01L29/788 , H01L29/94 , H01L27/115 , H01L29/423 , H01L29/78 , H01L29/66
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11558 , H01L29/42336 , H01L29/4236 , H01L29/42368 , H01L29/66181 , H01L29/66825 , H01L29/785 , H01L29/7881 , H01L29/7889 , H01L29/945
摘要： Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two-terminal programmable non-volatile device (200) includes a floating gate (210) disposed vertically about a substrate, wherein the floating gate comprises a first side (213), a second side (215), and a bottom portion (217). A source region (240) is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region (220) is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel (290) coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate. The channel can be recessed in the substrate or in a fin- shaped portion of the substrate. The gate insulating layer is thicker on the source side than on the drain side.
摘要翻译：垂直制造的非易失性存储器件在漏区和浮栅之间具有电容耦合。双端可编程非易失性装置（200）包括垂直于基底设置的浮动栅极（210），其中浮动栅极包括第一侧（213），第二侧（215）和底部部分（217））。源区域（240）耦合到第一端子并且形成为与浮置栅极的第一侧相邻。漏极区域（220）耦合到第二端子并且与浮动栅极的第二侧相邻地形成。非易失性器件包括耦合源区和漏区用于编程和擦除操作的通道（290）。漏极区域电容耦合到浮动栅极。通道可以凹陷在基板中或在基板的鳍状部分中。栅极绝缘层在源极侧比在漏极侧更厚。

6. 发明申请

WO2007080568A2 SYSTEM AND METHOD FOR INSPECTING WORKPIECES HAVING MICROSCOPIC FEATURES 审中-公开
标题翻译：用于检查具有微观特征的工件的系统和方法
公开(公告)号：WO2007080568A2
公开(公告)日：2007-07-19
申请号：PCT/IL2006/001418
申请日：2006-12-11
申请人： ORBOTECH LTD. , SAPHIER, Ofer , ADIN, Raanan , FISCH, David
发明人： SAPHIER, Ofer , ADIN, Raanan , FISCH, David
IPC分类号： G06K9/00
CPC分类号： G06K9/033 , G06K2209/19
摘要： Apparatus for high resolution processing of a generally planar workpiece having microscopic features to be imaged, comprising a video camera acquiring at least two candidate images of a microscopic portion on generally planar workpiece; a motion controller operative to effect motion, relative to the workpiece, of at least an optical element of the video camera along an optical axis extending generally normally to a location on a surface of the workpiece, the video camera acquiring the at least two candidate images at selected time intervals, each of the at least two candidate images differing by at least one image parameter; an image selector operative to select an individual image from among the at least two candidate images according to predefined criteria of image quality; and a selected image analyzer operative to analyze at least a portion of the individual image selected by the image selector.
摘要翻译：一种用于具有要成像的微观特征的大体平面的工件的高分辨率处理的装置，包括摄像机，其在大致平面的工件上获取微观部分的至少两个候选图像; 运动控制器，其操作以沿着通常大致延伸到工件表面上的位置的光轴实现至少摄像机的光学元件相对于工件的运动，摄像机获取至少两个候选图像在选定的时间间隔，所述至少两个候选图像中的每一个与至少一个图像参数不同; 图像选择器，用于根据图像质量的预定标准从所述至少两个候选图像中选择单个图像; 以及选择的图像分析器，用于分析由图像选择器选择的单个图像的至少一部分。

7. 发明申请

WO2008085701A3 METHOD AND APPARATUS FOR VARIABLE MEMORY CELL REFRESH 审中-公开
标题翻译：用于可变存储器单元刷新的方法和装置
公开(公告)号：WO2008085701A3
公开(公告)日：2009-02-12
申请号：PCT/US2007088529
申请日：2007-12-21
申请人： INNOVATIVE SILICON SA , FISCH DAVID , CARMAN ERIC
发明人： FISCH DAVID , CARMAN ERIC
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2207/104 , G11C2211/4016 , G11C2211/4067
摘要： The embodiments described herein allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. One embodiment includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or more memory cells of a memory array. The circuit integrates a refresh timer element with an event signal generator such that a refresh interval as defined by the refresh timer element is changed when events are detected that may change the data retention time of one or more memory cells. In various embodiments, one or more of the circuits is placed to monitor an entire memory array, different sub-arrays, or different portions of different sub-arrays. This allows additional refresh operations to be closely tied to actual events, thus increasing overall efficiency.
摘要翻译：这里描述的实施例允许使用存储器阵列或存储器本身的系统更有效地控制刷新间隔。这减少了备用电流和与刷新操作相关的开销。一个实施例包括可变模拟刷新信号产生电路，其启动对存储器阵列的一个或多个存储器单元的刷新操作。电路将刷新定时器元件与事件信号发生器集成，使得当检测到可能改变一个或多个存储器单元的数据保持时间的事件时，刷新定时器元件定义的刷新间隔被改变。在各种实施例中，放置一个或多个电路以监视整个存储器阵列，不同子阵列或不同子阵列的不同部分。这允许额外的刷新操作与实际事件紧密相关，从而提高整体效率。

8. 发明申请

WO2008150407A1 INTEGRATED CIRCUIT HAVING VOLTAGE GENERATION CIRCUITRY FOR MEMORY CELL ARRAY, AND METHOD OF OPERATING AND/OR CONTROLLING SAME 审中-公开
标题翻译：具有用于存储单元阵列的电压发生电路的集成电路及其操作和/或控制方法
公开(公告)号：WO2008150407A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/006743
申请日：2008-05-28
申请人： INNOVATIVE SILICON ISi SA , FISCH, David , BAUSER, Philippe
发明人： FISCH, David , BAUSER, Philippe
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C8/12 , G11C11/404 , G11C11/4076 , G11C2211/4016
摘要： A method of generating a voltage as well as an integrated circuit device having a memory cell array which Includes a plurality of memory cells, wherein each memory cell array including a plurality of memory cells, arranged in a matrix of rows and columns, and a plurality of bit lines, wherein each bit line includes a plurality of memory cells The integrated circuit further Includes voltage generation circuitry, coupled to a plurality of the bit lines, to apply a first voltage to a first group of associated bit lines, and apply a second voltage to a second group of associated bit lines, and generate a third voltage by connecting the first and second groups of associated bit lines, and output the third voltage Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry
摘要翻译：一种产生电压的方法以及具有包括多个存储单元的存储单元阵列的集成电路器件，其中每个存储单元阵列包括排列成行和列的矩阵的多个存储器单元，以及多个存储单元阵列的位线，其中每个位线包括多个存储单元。集成电路还包括耦合到多个位线的电压产生电路，以将第一电压施加到第一组关联位线，并施加第二组电压到第二组相关联的位线，并且通过连接第一组和第二组相关联的位线并产生第三电压，并输出第三电压。还公开了这种集成电路器件的操作和/或控制的方法以及这种电压产生电路

9. 发明申请

WO2008008329A3 MEMORY ARRAY HAVING A SEGMENTED BIT LINE ARCHITECTURE 审中-公开
标题翻译：内存阵列拥有一个分隔的位线架构
公开(公告)号：WO2008008329A3
公开(公告)日：2008-10-02
申请号：PCT/US2007015717
申请日：2007-07-10
申请人： INNOVATIVE SILICON SA , FISCH DAVID , BRON MICHEL
发明人： FISCH DAVID , BRON MICHEL
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/108 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C2207/002 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： An integrated memory circuit device having a memory cell array (102) including a plurality of bit lines (e.g., 32a, 32b) and a plurality of bit line segments (e.g., 32a1, 32b1) wherein each bit line segment is coupled to an associated bit line (32a, 32b). The memory cell array (102) further includes a plurality of memory cells (12), wherein each memory cell (12) includes a transistor (14) having a first region, a second region, a body region, and a gate coupled to an associated word line (28) via an associated word line segment. A first group of memory cells (12) is coupled to the first bit line (32a) via the first bit line segment (32a1) and a second group of memory cells (12) is coupled to the second bit line (32b) via the second bit line segment (32b1). A plurality of isolation circuits (104), disposed between each bit line segment (32a1, 32b1) and its associated bit line (32a, 32b), responsively connect the associated bit line segment to or disconnect the associated bit line segment (32a1, 32b1) from the associated bit line (32a, 32b).
摘要翻译：一种具有包括多个位线（例如，32a，32b）和多个位线段（例如，32a1,3b1）的存储单元阵列（102）的集成存储器电路器件，其中每个位线段耦合到相关联的位线（32a，32b）。存储单元阵列（102）还包括多个存储器单元（12），其中每个存储器单元（12）包括具有第一区域，第二区域，体区域和耦合到第一区域的栅极的晶体管（14）相关联的字线（28）。第一组存储器单元（12）经由第一位线段（32a1）耦合到第一位线（32a），并且第二组存储器单元（12）经由第二位线段第二位线段（32b1）。设置在每个位线段（32a1，32b1）和其相关联的位线（32a，32b）之间的多个隔离电路（104）响应地将相关联的位线段连接到或断开相关联的位线段（32a1,312b））从相关联的位线（32a，32b）。

10. 发明申请

WO2008008329A2 INTEGRATED CIRCUIT INCLUDING MEMORY ARRAY HAVING A SEGMENTED BIT LINE ARCHITECTURE AND METHOD OF CONTROLLING AND/OR OPERATING SAME 审中-公开
标题翻译：集成电路，包括具有分段位线架构的存储器阵列及其控制和/或操作的方法
公开(公告)号：WO2008008329A2
公开(公告)日：2008-01-17
申请号：PCT/US2007/015717
申请日：2007-07-10
申请人： INNOVATIVE SILICON S.A. , FISCH, David , BRON, Michel
发明人： FISCH, David , BRON, Michel
IPC分类号： G11C5/06
CPC分类号： H01L27/108 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C2207/002 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is coupled to an associated bit line. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, responsively connect the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.
摘要翻译：具有包括多个位线（例如，第一和第二位线）和多个位线段（例如，第一和第二位线）的存储单元阵列的集成电路器件（例如，逻辑器件或存储器件）段），其中每个位线段耦合到相关联的位线。存储单元阵列还包括多个存储单元，其中每个存储单元包括具有第一区域，第二区域，体区域和经由相关联的字线段耦合到关联字线的栅极的晶体管。第一组存储器单元经由第一位线段耦合到第一位线，并且第二组存储器单元经由第二位线段耦合到第二位线。设置在每个位线段与其相关位线之间的多个隔离电路响应地将相关联的位线段连接到相关联的位线段或将其与相关联的位线断开。

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