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1. 发明申请

WO2009034362A1 SUBSTRATE FOR HIGH FREQUENCY INTEGRATED CIRCUIT 审中-公开
标题翻译：高频集成电路基板
公开(公告)号：WO2009034362A1
公开(公告)日：2009-03-19
申请号：PCT/GB2008/003131
申请日：2008-09-15
申请人： ISIS INNOVATION LIMITED , WILSHAW, Peter, Richard , MALLIK, Kanad , FALSTER, Robert, James
发明人： WILSHAW, Peter, Richard , MALLIK, Kanad , FALSTER, Robert, James
IPC分类号： H01L21/22 , H01L21/762 , H01L29/167
CPC分类号： H01L21/221 , H01L21/76251 , H01L29/167
摘要： A substrate for a high frequency integrated circuit is described, comprising: a silicon wafer comprising impurities of a type that form one or more deep energy levels within the band gap of the silicon forming the silicon wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and an electrically insulating silicon oxide layer, formed on a surface of the silicon wafer and providing an outer surface on which a device layer may be formed, said silicon oxide layer having the property of preventing diffusion of said impurities through it. Alternative arrangements may use a different diffusion barrier layer between the silicon wafer and device layer with an additional diffusion barrier layer encapsulating the silicon wafer layer and/or device layer. Associated methods of manufacture are described.
摘要翻译：描述了一种用于高频集成电路的衬底，包括：硅晶片，其包括在形成硅晶片的硅的带隙内形成一个或多个深能级的类型的杂质，其中所述深能级中的至少一个如果电平是施主电平或离电荷带至少0.3eV远离导带至少0.3eV，如果电平是受体电平; 以及电绝缘性氧化硅层，其形成在所述硅晶片的表面上并且提供可在其上形成器件层的外表面，所述氧化硅层具有防止所述杂质通过其扩散的性质。可选择的布置可以在硅晶片和器件层之间使用不同的扩散阻挡层，其中附加的扩散阻挡层封装硅晶片层和/或器件层。描述了相关的制造方法。

2. 发明申请

WO2006125069A2 A HIGH RESISTIVITY SILICON STRUCTURE AND A PROCESS FOR THE PREPARATION THEREOF 审中-公开
标题翻译：高电阻硅结构及其制备方法
公开(公告)号：WO2006125069A2
公开(公告)日：2006-11-23
申请号：PCT/US2006/019207
申请日：2006-05-18
申请人： MEMC ELECTRONIC MATERIALS, INC. , FALSTER, Robert, J. , VORONKOV, Vladimir, V. , VORONKOVA, Galina, I. , BATUNINA, Anna, V.
发明人： FALSTER, Robert, J. , VORONKOV, Vladimir, V. , VORONKOVA, Galina, I. , BATUNINA, Anna, V.
IPC分类号： C30B33/00 , C30B29/06 , C30B33/02 , H01L21/324
CPC分类号： H01L21/324 , C30B29/06 , C30B33/00 , C30B33/02 , H01L21/3225
摘要： The present invention generally relates to a high resistivity CZ silicon wafer, or a high resistivity silicon structure derived therefrom, and a process for the preparation thereof. In particular, the high resistivity silicon structure comprises a large diameter CZ silicon wafer as the substrate thereof, wherein the resistivity of the substrate wafer is decoupled from the concentration of acceptor atoms (e.g., boron) therein, the resistivity of the substrate being substantially greater than the resistivity as calculated based on the concentration of said acceptor atoms therein.
摘要翻译：本发明一般涉及一种高电阻率CZ硅晶片或其衍生的高电阻率硅结构及其制备方法。特别地，高电阻率硅结构包括作为其基底的大直径CZ硅晶片，其中衬底晶片的电阻率与其中的受主原子（例如硼）的浓度分离，衬底的电阻率基本上更大比基于其中的所述受主原子的浓度计算的电阻率。

3. 发明申请

WO2012167104A4 PROCESSES FOR SUPPRESSING MINORITY CARRIER LIFETIME DEGRADATION IN SILICON WAFERS 审中-公开
公开(公告)号：WO2012167104A4
公开(公告)日：2012-12-06
申请号：PCT/US2012/040492
申请日：2012-06-01
申请人： MEMC SINGAPORE PTE, LTD. , FALSTER, Robert J. , VORONKOV, Vladimir V.
发明人： FALSTER, Robert J. , VORONKOV, Vladimir V.
IPC分类号： H01L31/18
摘要： Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.

4. 发明申请

WO2009006183A2 DIFFUSION CONTROL IN HEAVILY DOPED SUBSTRATES 审中-公开
标题翻译：扩散控制在重掺杂基体中的应用
公开(公告)号：WO2009006183A2
公开(公告)日：2009-01-08
申请号：PCT/US2008068287
申请日：2008-06-26
申请人： MEMC ELECTRONIC MATERIALS , VORONKOV VLADIMIR V , FALSTER ROBERT J , MOIRAGHI LUCA , LEE DONG MYUN , CHO CHANRAE , RAVANI MARCO
发明人： FALSTER ROBERT J , MOIRAGHI LUCA , LEE DONG MYUN , CHO CHANRAE , RAVANI MARCO
IPC分类号： H01L21/22 , H01L21/20 , H01L21/265 , H01L21/322
CPC分类号： H01L21/2205 , H01L21/26506 , H01L21/3225 , Y10T428/249961
摘要： This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.
摘要翻译：本发明一般涉及在具有重掺杂硅衬底和轻掺杂硅外延层的外延硅晶片的衬底/外延层界面附近抑制硅自填隙扩散的方法。通过包含位错环的硅自填隙吸收层抑制到外延层中的间隙扩散。

5. 发明申请

WO2009006182A1 SUPPRESSION OF OXYGEN PRECIPITATION IN HEAVILY DOPED SINGLE CRYSTAL SILICON SUBSTRATES 审中-公开
标题翻译：抑制重金属单晶硅基质中的氧沉降
公开(公告)号：WO2009006182A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/068284
申请日：2008-06-26
申请人： MEMC ELECTRONIC MATERIALS, INC. , FALSTER, Robert, J. , MOIRAGHI, Luca , LEE, Dong Myun , CHO, Chanrae , RAVANI, Marco
发明人： FALSTER, Robert, J. , MOIRAGHI, Luca , LEE, Dong Myun , CHO, Chanrae , RAVANI, Marco
IPC分类号： H01L21/322
CPC分类号： H01L21/3225 , Y10T428/21
摘要： This invention generally relates to a process for suppressing oxygen precipitation in epitaxial silicon wafers having a heavily doped silicon substrate and a lightly N-doped silicon epitaxial layer by dissolving existing oxygen clusters and precipitates within the substrate. Furthermore, the formation of oxygen precipitates is prevented upon subsequent oxygen precipitation heat treatment.
摘要翻译：本发明一般涉及一种通过将现有的氧簇和沉淀物溶解在衬底中来抑制具有重掺杂硅衬底和轻掺杂N掺杂硅外延层的外延硅晶片中的氧沉淀的方法。此外，在随后的氧沉淀热处理时，防止形成氧析出物。

6. 发明申请

WO1992009101A1 PROCESS FOR ACHIEVING CONTROLLED PRECIPITATION PROFILES IN SILICON WAFERS 审中-公开
标题翻译：在硅陶瓷中实现控制退化配置文件的过程
公开(公告)号：WO1992009101A1
公开(公告)日：1992-05-29
申请号：PCT/IT1991000095
申请日：1991-11-11
申请人： MEMC ELECTRONIC MATERIALS S.P.A. , FALSTER, Robert , FERRERO, Giancarlo , FISHER, Graham , OLMO, Massimiliano , PAGANI, Marco
发明人： MEMC ELECTRONIC MATERIALS S.P.A.
IPC分类号： H01L21/322
CPC分类号： H01L21/3225
摘要： The object of the invention is a process for the treatment of silicon wafers to achieve therein controlled precipitation profiles for the manufacture of electronic components, comprising the following fundamental operations: a) subjecting the wafers to a preliminary thermal treatment, at a temperature between 950 DEG C and 1150 DEG C, in particular at about 1100 DEG C, for a duration of about 15 minutes; b) after a standard chemical corrosion (etching) treatment, subjecting pairs of coupled wafers in a close reciprocal thermal contact to a rapid thermal annealing treatment, at a temperature between 1200 DEG C and 1275 DEG C for a duration of some tens of seconds; c) subjecting the wafers to a further extended thermal treatment at a temperature between 900 DEG C and 1000 DEG C, and, finally, d) extracting the wafers from the furnace and subjecting the surfaces that were in a close reciprocal contact during the rapid annealing treatment to a surface polishing. The resulting wafers have a profile of the density of the precipitates that presents a concentration peak in proximity to a surface (trapping zone) and a very low concentration plateau in proximity to the other surface (active zone).
摘要翻译：本发明的目的是一种用于处理硅晶片以在其中实现用于制造电子部件的受控沉淀曲线的方法，其包括以下基本操作：a）在950℃之间的温度下对晶片进行预热处理 C和1150℃，特别是约1100℃，持续约15分钟; b）在进行标准化学腐蚀（蚀刻）处理之后，在1200℃至1275℃的温度下，将几对耦合的晶片在紧密相互热接触下进行快速热退火处理，持续数十秒; c）在900℃至1000℃的温度下对晶片进行进一步的延伸热处理，最后，d）从炉中提取晶片并在快速退火期间使彼此紧密相互接触的表面经受处理到表面抛光。所得到的晶片具有在表面（捕获区域）附近呈现浓度峰值和在另一表面（活性区域）附近的非常低的浓度平台的沉淀物的密度分布。

7. 发明申请

WO2012167104A1 PROCESSES FOR SUPPRESSING MINORITY CARRIER LIFETIME DEGRADATION IN SILICON WAFERS 审中-公开
标题翻译：阻止少量运载火箭降解硅氧烷的方法
公开(公告)号：WO2012167104A1
公开(公告)日：2012-12-06
申请号：PCT/US2012040492
申请日：2012-06-01
申请人： MEMC SINGAPORE PTE LTD , FALSTER ROBERT J , VORONKOV VLADIMIR V
发明人： FALSTER ROBERT J , VORONKOV VLADIMIR V
IPC分类号： H01L31/18
CPC分类号： H01L29/16 , H01L21/3221 , H01L31/1804 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.
摘要翻译：公开了抑制硅晶片中的少数载流子寿命劣化的方法。该方法包括骤冷冷却晶片以增加硅晶片中的纳米沉淀物的密度以及间隙原子被纳米沉淀物消耗的速率。

8. 发明申请

WO2007056745A2 ARSENIC AND PHOSPHORUS DOPED SILICON WAFER SUBSTRATES HAVING INTRINSIC GETTERING 审中-公开
标题翻译：具有本征吸收的砷和磷掺杂的硅晶片基材
公开(公告)号：WO2007056745A2
公开(公告)日：2007-05-18
申请号：PCT/US2006060651
申请日：2006-11-08
申请人： MEMC ELECTRONIC MATERIALS , FALSTER ROBERT J , VORONKOV VLADIMIR , BORIONETTI GABRIELLA
发明人： FALSTER ROBERT J , VORONKOV VLADIMIR , BORIONETTI GABRIELLA
CPC分类号： H01L21/3225 , C30B29/06 , C30B33/02
摘要： A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
摘要翻译：一种制备低电阻率砷或磷掺杂（N + / N ++）硅晶片的方法，其在基本上任何任意电子器件制造工艺的热处理循环过程中可靠地形成氧沉淀。

9. 发明申请

WO2006125069A3 A HIGH RESISTIVITY SILICON STRUCTURE AND A PROCESS FOR THE PREPARATION THEREOF 审中-公开
标题翻译：高电阻硅结构及其制备方法
公开(公告)号：WO2006125069A3
公开(公告)日：2007-01-18
申请号：PCT/US2006019207
申请日：2006-05-18
申请人： MEMC ELECTRONIC MATERIALS , FALSTER ROBERT J , VORONKOV VLADIMIR V , VORONKOVA GALINA I , BATUNINA ANNA V
发明人： FALSTER ROBERT J , VORONKOV VLADIMIR V , VORONKOVA GALINA I , BATUNINA ANNA V
IPC分类号： C30B33/00 , C30B29/06 , C30B33/02 , H01L21/324
CPC分类号： H01L21/324 , C30B29/06 , C30B33/00 , C30B33/02 , H01L21/3225
摘要： The present invention generally relates to a high resistivity CZ silicon wafer, or a high resistivity silicon structure derived therefrom, and a process for the preparation thereof. In particular, the high resistivity silicon structure comprises a large diameter CZ silicon wafer as the substrate thereof, wherein the resistivity of the substrate wafer is decoupled from the concentration of acceptor atoms (e.g., boron) therein, the resistivity of the substrate being substantially greater than the resistivity as calculated based on the concentration of said acceptor atoms therein.
摘要翻译：本发明一般涉及一种高电阻率CZ硅晶片或其衍生的高电阻率硅结构及其制备方法。特别地，高电阻率硅结构包括作为其基底的大直径CZ硅晶片，其中衬底晶片的电阻率与其中的受主原子（例如，硼）的浓度分离，衬底的电阻率基本上更大比基于其中所述受主原子的浓度计算的电阻率。

10. 发明申请

WO2014200686A1 OXYGEN PRECIPITATION IN HEAVILY DOPED SILICON WAFERS SLICED FROM INGOTS GROWN BY THE CZOCHRALSKI METHOD 审中-公开
标题翻译：由CZOCHRALSKI方法生成的酸性硅酸盐沉淀的氧化硅沉淀
公开(公告)号：WO2014200686A1
公开(公告)日：2014-12-18
申请号：PCT/US2014/039363
申请日：2014-05-23
申请人： SUNEDISON SEMICONDUCTOR LIMITED , FALSTER, Robert J.
发明人： FALSTER, Robert J. , VORONKOV, Vladimir V.
IPC分类号： H01L21/322
CPC分类号： H01L29/36 , H01L21/02694 , H01L21/223 , H01L21/3225
摘要： A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
摘要翻译：提供了具有晶片电阻率小于约10毫欧姆 - 厘米的单晶硅晶片中的氧沉淀控制方法，使晶片具有从中心轴到圆周边缘均匀高的氧沉淀性能。单晶硅晶片包括选自碳，砷和锑的另外的掺杂剂。

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