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1. 发明申请

WO2009057051A2 PASSIVE HARMONIC-REJECTION MIXER 审中-公开
标题翻译：被动谐波抑制混频器
公开(公告)号：WO2009057051A2
公开(公告)日：2009-05-07
申请号：PCT/IB2008/054466
申请日：2008-10-29
申请人： NXP B.V. , BREKELMANS, Johannes, H. A. , DE JONG, Gerben, W. , EL WAFFAOUI, Rachid , JEURISSEN, Dennis , VAN SINDEREN, Jan , LEE, Simon, WK,
发明人： BREKELMANS, Johannes, H. A. , DE JONG, Gerben, W. , EL WAFFAOUI, Rachid , JEURISSEN, Dennis , VAN SINDEREN, Jan , LEE, Simon, WK,
IPC分类号： H03D7/14
CPC分类号： H03D7/165 , H03D7/18 , H03D2200/0082 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
摘要翻译：一种包括无源谐波抑制混频器的电子设备。无源谐波抑制混频器具有连接到多个子混频器级的输入，并且子混频器级连接到用于产生输出的求和模块。每个子混合级包括门控模块和相应的放大器，门控模块适于在控制信号的控制下选择性地传递具有反相极性的输入信号或输入信号。

2. 发明申请

WO2008018033A2 SIGNAL PROCESSOR COMPRISING A FREQUENCY CONVERTER 审中-公开
标题翻译：包含频率转换器的信号处理器
公开(公告)号：WO2008018033A2
公开(公告)日：2008-02-14
申请号：PCT/IB2007/053137
申请日：2007-08-08
申请人： NXP B.V. , VAN ZEIJL, Paulus, T., M. , DE JONG, Gerben, W. , JEURISSEN, Dennis
发明人： VAN ZEIJL, Paulus, T., M. , DE JONG, Gerben, W. , JEURISSEN, Dennis
IPC分类号： H03D7/14
CPC分类号： H03D7/166 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/165 , H03D2200/0025
摘要： A signal processor includes a frequency converter of the multiphase type. A first phase mixer (SWC1, TIS1) has a pair of switches (M11, M12). A second phase mixer (SWC2, TIS2) also has a pair of switches (M21, M22). The pair of switches of the first phase mixer and the pair of switches of the second phase mixer have a joint common switch node (CN1). A local oscillator generates an individual mixer driver signal (MD1+, MD1-, MDQ+, MDQ-) for each switch (M11, M12, M21, M22) in the aforementioned pairs. Each individual mixer driver signal comprises periodically occurring pulses, which are phase shifted with respect to the periodically occurring pulses in the other individual mixer driver signals. Preferably, there is substantially no overlap between the periodically occurring pulses in the individual mixer driver signals.
摘要翻译：信号处理器包括多相类型的变频器。第一相混频器（SWC1，TIS1）具有一对开关（M11，M12）。第二相位混频器（SWC2，TIS2）也有一对开关（M21，M22）。第一相位混频器的这对开关和第二相位混频器的一对开关具有一个共同的公共开关节点（CN1）。本地振荡器为前述对中的每个开关（M11，M12，M21，M22）生成单独的混频器驱动器信号（MD1 +，MD1-，MDQ +，MDQ-）。每个单独的混频器驱动器信号包括周期性发生的脉冲，其相对于其他单独的混频器驱动器信号中的周期性发生的脉冲而被相移。优选地，各个混合器驱动器信号中的周期性出现的脉冲之间基本上没有重叠。

3. 发明申请

WO2007069191A2 MULTI-MODE MODULATION APPARATUS 审中-公开
标题翻译：多模式调制装置
公开(公告)号：WO2007069191A2
公开(公告)日：2007-06-21
申请号：PCT/IB2006/054760
申请日：2006-12-12
申请人： NXP B.V. , VROMANS, Jan , DE JONG, Gerben, W. , RUITENBURG, Leonardus, J., M.
发明人： VROMANS, Jan , DE JONG, Gerben, W. , RUITENBURG, Leonardus, J., M.
IPC分类号： H04L27/36
CPC分类号： H04L27/366 , H03F1/0205 , H03F1/3211 , H03F1/3241 , H03F1/3288 , H03F3/217 , H03F3/24 , H03F3/45085 , H03F2200/351
摘要： The present invention relates to a multi-mode modulation apparatus and a method of modulating a carrier signal by a baseband signal in at least two modulation modes. The phase of the carrier signal is modulated in response to a first control signal derived from the baseband signal to obtain a first phase-modulated signal, and the phase of the carrier signal is additionally modulated in response to a second control signal derived from the baseband signal to obtain a second phase-modulated signal, wherein combination of the first and second phase-modulated signals is controlled to select one of the at least two modulation modes. Thereby, information of different components (e.g. phase and envelope) of the baseband signal can be phase-modulated and combined in a suitable manner, so that over- sampling and highly linear triangular or saw-tooth signals are no longer required. Moreover, the controlled combination provides a flexible multi-mode modulation scheme.
摘要翻译：本发明涉及一种多模调制装置和一种以至少两种调制模式通过基带信号调制载波信号的方法。响应于从基带信号导出的第一控制信号来调制载波信号的相位以获得第一相位调制信号，并且响应于从基带导出的第二控制信号附加地调制载波信号的相位信号以获得第二相位调制信号，其中控制第一和第二相位调制信号的组合以选择至少两个调制模式之一。因此，基带信号的不同分量（例如相位和包络）的信息可以被相位调制并以适当的方式组合，使得不再需要过采样和高度线性的三角形或锯齿信号。此外，受控组合提供灵活的多模式调制方案。

4. 发明申请

WO2004112136A1 ELECTRONIC DEVICE 审中-公开
标题翻译：电子设备
公开(公告)号：WO2004112136A1
公开(公告)日：2004-12-23
申请号：PCT/IB2004/050864
申请日：2004-06-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DEKKER, Ronald , HURKX, Godefridus, A., M. , JANSMAN, Andreas, B., M. , KEMMEREN, Antonius, L., A., M. , BERGERVOET, Jozef, R., M. , DE JONG, Gerben, W. , STEK, Aalbert
发明人： DEKKER, Ronald , HURKX, Godefridus, A., M. , JANSMAN, Andreas, B., M. , KEMMEREN, Antonius, L., A., M. , BERGERVOET, Jozef, R., M. , DE JONG, Gerben, W. , STEK, Aalbert
IPC分类号： H01L25/065
CPC分类号： H01L21/6835 , H01L23/5389 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L29/0657 , H01L2221/68377 , H01L2224/16 , H01L2224/16227 , H01L2224/24137 , H01L2224/24147 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2224/92244 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12032 , H01L2924/12043 , H01L2924/1305 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15192 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： The electronic device of the invention comprises a substrate with semiconductor elements, in which substrate one or more cavities are provided. Further active devices are provided in the cavities and coupled to the semiconductor elements through one common multilayer interconnect structure.
摘要翻译：本发明的电子器件包括具有半导体元件的衬底，其中提供有一个或多个腔体。另外的有源器件设置在空腔中，并通过一个共同的多层互连结构耦合到半导体元件。

5. 发明申请

WO2004110086A1 FREQUENCY MULTIPLEXED ARCHITECTURE 审中-公开
标题翻译：频率多路复用架构
公开(公告)号：WO2004110086A1
公开(公告)日：2004-12-16
申请号：PCT/IB2004/050776
申请日：2004-05-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , COLLADOS ASENSIO, Manel , DE JONG, Gerben, W.
发明人： COLLADOS ASENSIO, Manel , DE JONG, Gerben, W.
IPC分类号： H04Q7/30
CPC分类号： H04B1/006 , H04B1/005 , H04B1/406
摘要： A receiver (10) is arranged to simultaneously receive at least a first (S1) radio frequency signal having a first frequency band (1) and a second radio frequency signal (S3) having a second frequency band (3) that is at least partly overlapping the first frequency band (1). The receiver has frequency down-conversion means (32,33) for frequency down converting the at least first (S1) and second radio frequency signals (S3) to at least a first (S2) and a second (S4) lower frequency signal and multiplexing means (34) for sequentially multiplexing the at least first (S2) and second lower frequency signals (S4) into a frequency multiplexed signal (S5).
摘要翻译：接收机（10）被布置成同时接收具有第一频带（1）的第一（S1）射频信号和具有至少部分地具有第二频带（3）的第二射频信号（S3）与第一频带（1）重叠。接收机具有频率下变频装置（32,33），用于将至少第一（S1）和第二射频信号（S3）降频转换成至少第一（S2）和第二（S4）较低频率信号，以及用于将所述至少第一（S2）和第二低频信号（S4）顺序复用为频率复用信号（S5）的多路复用装置（34）。

6. 发明申请

WO2004015692A2 OPTICAL DISK SYSTEM WITH DELAYLINELESS DELAY-DIFFERENCE DETECTOR 审中-公开
标题翻译：具有延迟延迟差分检测器的光盘系统
公开(公告)号：WO2004015692A2
公开(公告)日：2004-02-19
申请号：PCT/IB2003/003293
申请日：2003-07-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VOORMAN, Johannes, O. , DE JONG, Gerben, W. , BREKELMANS, Johannes, H., A.
发明人： VOORMAN, Johannes, O. , DE JONG, Gerben, W. , BREKELMANS, Johannes, H., A.
IPC分类号： G11B7/00
CPC分类号： G11B7/131 , G11B7/0901
摘要： Optical disk systems comprising photo detectors (1) for detecting optical disks comprising amplifiers and slicers (2-5) and delay-difference detectors (6) for detecting delay differences in sliced amplified detection signals are improved by installing delaylineless delay-difference detectors (6) comprising combinatorial-logic circuits (7,8) like inverters, ORs, NORs, ANDs, NANDs and sequential-logic circuits (11-18) like SetResetFlipFlops. Without the prior art delay lines, said delay-difference detectors (6) are of a lower complexity and low costly and can be well integrated. By introducing a first pair of sequential-logic circuits (11,12,15,16) for detecting delay differences between rising edges and a second pair of sequential-logic circuits (13,14,17,18) for detecting delay differences between falling edges, both kinds of edges are being used and the influence of time-jitter is less compared to the situation where just one kind of edge is used. Said delay-difference detector (6) further comprises an analog adder/subtracter (9) for adding/ subtracting sequential-logic circuit output signals and low pass filter(s) (10) located before or after said adder/subtracter (9).
摘要翻译：包括用于检测包括放大器和限幅器（2-5）的光盘的光检测器（1）和用于检测分片放大的检测信号中的延迟差的延迟差检测器（6），通过安装延迟无延迟差分检测器）包括类似反相器，OR，NOR，AND的组合逻辑电路（7,8），NAND和诸如SetResetFlipFlops的顺序逻辑电路（11-18）。在没有现有技术的延迟线的情况下，所述延迟差检测器（6）具有较低的复杂性并且成本低且可以很好地集成。通过引入用于检测上升沿之间的延迟差的第一对顺序逻辑电路（11,12,15,16）和用于检测下降沿之间的延迟差的第二对顺序逻辑电路（13,14,17,18）边缘，正在使用两种边缘，并且与仅使用一种边缘的情况相比，时间抖动的影响较小。所述延迟差检测器（6）还包括用于加/减顺序逻辑电路输出信号的模拟加法器/减法器（9）和位于所述加法器/减法器（9）之前或之后的低通滤波器（10）。

7. 发明申请

WO2009057051A3 PASSIVE HARMONIC-REJECTION MIXER 审中-公开
标题翻译：被动谐波抑制混频器
公开(公告)号：WO2009057051A3
公开(公告)日：2010-04-15
申请号：PCT/IB2008054466
申请日：2008-10-29
申请人： NXP BV , BREKELMANS JOHANNES H A , DE JONG GERBEN W , EL WAFFAOUI RACHID , JEURISSEN DENNIS , VAN SINDEREN JAN , LEE SIMON WK
发明人： BREKELMANS JOHANNES H A , DE JONG GERBEN W , EL WAFFAOUI RACHID , JEURISSEN DENNIS , VAN SINDEREN JAN , LEE SIMON WK
IPC分类号： H03D7/16 , H03D7/18
CPC分类号： H03D7/165 , H03D7/18 , H03D2200/0082 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
摘要翻译：一种包括无源谐波抑制混频器的电子设备。无源谐波抑制混频器具有连接到几个子混频器级的输入，并且子混频器级连接到用于产生输出的求和模块。每个子混合级包括门控模块和相应的放大器，门控模块适于在控制信号的控制下选择性地传递具有反相极性的输入信号或输入信号。

8. 发明申请

WO2009144642A2 LOW-1/F-NOISE LOCAL OSCILLATOR FOR NON-OVERLAPPING DIFFERENTIAL I/Q SIGNALS 审中-公开
标题翻译：用于非重叠差分I / Q信号的低1 / F噪声局部振荡器
公开(公告)号：WO2009144642A2
公开(公告)日：2009-12-03
申请号：PCT/IB2009/052133
申请日：2009-05-21
申请人： NXP B.V. , DE JONG, Gerben, W. , JEURISSEN, Dennis
发明人： DE JONG, Gerben, W. , JEURISSEN, Dennis
IPC分类号： H03K17/28 , H03K5/04 , H03K5/156 , H03D7/16
CPC分类号： H03D7/166 , H03K5/1565 , H03K17/28
摘要： The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before- make (BBM) circuit ensures that the differential I/Q signals (LO_0, LO_90, LO_180, LO_270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-overlapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (Δ) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT_0, LT_90, LT_180, LT_270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (Δ) equal to zero. Thereby, the combined action of the BBM circuit and the feedback loops results in four non-overlapping differential I/Q signals (LO_0, LO_90, LO_180, LO_270) with constant and mutually equal duty cycles, and fixed and well-defined relative positions.
摘要翻译：本发明涉及如上所述的用于产生不重叠和免疫-1-f噪声信号的电路装置（300）。断开（BBM）电路确保驱动RF中的混频器（16A，16B）的晶体管（M11，M12，M21，M22）的差分I / Q信号（LO_0，LO_90，LO_180，LO_270）接收器（200）不重叠，以便随时只有这些晶体管中的一个导通。测量每个驱动信号的占空比，并且通过相应的差分放大器（38A-38D）确定与两个后续LO相位相对应的占空比中的差（α）。每个差分放大器被配置为具有电流输出（LT_0，LT_90，LT_180，LT_270），然后将其反馈到与第一LO相对应的输入缓冲器（30A-30D）的输入，以便调整其逻辑阈值（LT）电平，并使差值（？）等于零。因此，BBM电路和反馈环路的组合动作产生具有恒定且相互相等的占空比的四个不重叠的差分I / Q信号（LO_0，LO_90，LO_180，LO_270）以及固定且明确定义的相对位置。

9. 发明申请

WO2008084419A2 ENHANCED PREDISTORTION FOR SLEWING CORRECTION 审中-公开
标题翻译：增强校正校正
公开(公告)号：WO2008084419A2
公开(公告)日：2008-07-17
申请号：PCT/IB2008/050017
申请日：2008-01-04
申请人： NXP B.V. , VROMANS, Jan, S. , DEKKERS, Jan, C., A. , DE JONG, Gerben, W.
发明人： VROMANS, Jan, S. , DEKKERS, Jan, C., A. , DE JONG, Gerben, W.
IPC分类号： H03K7/10 , H03K6/04 , H03C3/02
CPC分类号： H03C3/04 , H03C5/00 , H03F1/3282
摘要： The present invention relates to a circuit arrangement and method of applying predistortion to a baseband signal used for modulating a pulse-shaped signal, wherein an envelope information of the baseband signal is detected and slewing distortions of the pulse- shaped signal are reduced by applying at least one of a phase modulation and a duty cycle 5 modulation to the baseband signal as additional predistortion in response to the detected envelope information. Thereby, slewing distortions in the pulse-shaped signal are removed or at least reduced.
摘要翻译：本发明涉及一种将预失真应用于用于调制脉冲信号的基带信号的电路装置和方法，其中基带信号的包络信息被检测并且脉冲形信号的回转失真通过施加在对基带信号进行相位调制和占空比5调制中的至少一个作为响应于检测到的包络信息的附加预失真。因此，脉冲形信号中的回转失真被去除或至少减少。

10. 发明申请

WO2008018033A3 SIGNAL PROCESSOR COMPRISING A FREQUENCY CONVERTER 审中-公开
标题翻译：包含频率转换器的信号处理器
公开(公告)号：WO2008018033A3
公开(公告)日：2008-04-03
申请号：PCT/IB2007053137
申请日：2007-08-08
申请人： NXP BV , VAN ZEIJL PAULUS T M , DE JONG GERBEN W , JEURISSEN DENNIS
发明人： VAN ZEIJL PAULUS T M , DE JONG GERBEN W , JEURISSEN DENNIS
IPC分类号： H03D7/14
CPC分类号： H03D7/166 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/165 , H03D2200/0025
摘要： A signal processor includes a frequency converter of the multiphase type. A first phase mixer (SWC1, TIS1) has a pair of switches (M11, M12). A second phase mixer (SWC2, TIS2) also has a pair of switches (M21, M22). The pair of switches of the first phase mixer and the pair of switches of the second phase mixer have a joint common switch node (CN1). A local oscillator generates an individual mixer driver signal (MD1+, MD1-, MDQ+, MDQ-) for each switch (M11, M12, M21, M22) in the aforementioned pairs. Each individual mixer driver signal comprises periodically occurring pulses, which are phase shifted with respect to the periodically occurring pulses in the other individual mixer driver signals. Preferably, there is substantially no overlap between the periodically occurring pulses in the individual mixer driver signals.
摘要翻译：信号处理器包括多相型变频器。第一相混频器（SWC1，TIS1）具有一对开关（M11，M12）。第二相混频器（SWC2，TIS2）也具有一对开关（M21，M22）。第一相混频器的一对开关和第二相混频器的一对开关具有联合公共开关节点（CN1）。本地振荡器在上述对中为每个开关（M11，M12，M21，M22）产生单独的混频器驱动器信号（MD1 +，MD1，MDQ +，MDQ-）。每个单独的混频器驱动器信号包括相对于其它单独混频器驱动器信号中周期性发生的脉冲相移的周期性发生的脉冲。优选地，各个混频器驱动器信号中周期性发生的脉冲之间基本上不存在重叠。

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