专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011045718A1 DUAL DRIVE EXTERNALLY MODULATED LASER 审中-公开
标题翻译：双驱动外部调制激光
公开(公告)号：WO2011045718A1
公开(公告)日：2011-04-21
申请号：PCT/IB2010/054558
申请日：2010-10-08
申请人： COREOPTICS INC , WHITEAWAY, James , KUPFER, Theo , RAABE, Christian
发明人： WHITEAWAY, James , KUPFER, Theo , RAABE, Christian
IPC分类号： H04B10/155
CPC分类号： H04B10/5051 , H04B10/504
摘要： A method of generating a signal in an optical transmitter comprising a directly modulated laser and an amplitude modulator for modulating the output of the laser. The method comprises the steps of applying a first modulation signal representing data to be transmitted to the current of the laser such that the output frequency of the laser is modulated, and applying a second modulation signal representing the data to be transmitted to the amplitude modulator such that the amplitude of the laser output is modulated.
摘要翻译：一种在光发射机中产生信号的方法，包括直接调制的激光器和用于调制激光器的输出的幅度调制器。该方法包括以下步骤：将表示要发送的数据的第一调制信号施加到激光器的电流，使得激光器的输出频率被调制，以及将表示待传输的数据的第二调制信号施加到幅度调制器，激光输出的幅度被调制。

2. 发明申请

WO02091649A3 CLOCK RECOVERY CIRCUIT 审中-公开
标题翻译：时钟恢复电路
公开(公告)号：WO02091649A3
公开(公告)日：2003-03-20
申请号：PCT/US0213937
申请日：2002-05-03
申请人： COREOPTICS INC
发明人： DORSCHKY CLAUS , KUPFER THEODOR
IPC分类号： H03L7/07 , H03L7/095 , H03L7/10 , H03L7/107 , H04L7/00 , H04L7/033 , H03K5/01
CPC分类号： H03L7/07 , H03L7/095 , H03L7/10 , H03L7/107 , H04L7/0004 , H04L7/033
摘要： A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase-locked loop circuit (104) operating in a fast acquisition mode for acquiring the clock from a data signal (D), a second phase locked loop circuit (102) for operating in a normal mode to recover the clock signal (Crec) in the digital data signal once the first phase locked loop circuit (104) has acquired the clock from the data signal, and a switch circuit (sw1, sw2, sw3) responsive to switch control signals for switching between the first phase locked loop circuit (104) and the second phase locked loop circuit (102) after the first phase locked loop circuit (104) has acquired the digital data signal.
摘要翻译：公开了一种与具有低信噪比的高速数据信号一起使用的时钟恢复电路。电路包括以快速获取模式操作的第一锁相环电路（104），用于从数据信号（D）获取时钟;第二锁相环电路（102），用于在正常模式下操作以恢复时钟一旦第一锁相环电路（104）从数据信号中获取时钟，数字数据信号中的信号（Crec）和响应于切换控制信号的开关电路（sw1，sw2，sw3），用于在第一相在第一锁相环电路（104）获取数字数据信号之后，锁定环电路（104）和第二锁相环电路（102）。

3. 发明申请

WO2008098934A1 TAIL EXTRAPOLATOR AND METHOD 审中-公开
标题翻译：尾部提取器和方法
公开(公告)号：WO2008098934A1
公开(公告)日：2008-08-21
申请号：PCT/EP2008/051684
申请日：2008-02-12
申请人： COREOPTICS INC. , STOJANOVIC, Nebojsa
发明人： STOJANOVIC, Nebojsa
IPC分类号： H04L1/20
CPC分类号： H04L1/20
摘要： This invention discloses a method which comprises quantizing an input signal. The number of equal quantized values during a period of time is counted thereby obtaining said number of counts (22). The counts exceeding a count threshold (21) being defined as reliable counts, the counts lower than or equal to the count threshold being defined as unreliable counts. Two unreliable counts are calculated using a lower and a higher value for a first parameter in an extrapolating function. The first parameter is considered equivalent to the lower value if the two unreliable counts differ less than or equal to a count difference (ε). The invention further discloses a corresponding tail extrapolator.
摘要翻译：本发明公开了一种包括量化输入信号的方法。计数一段时间内的相等量化值的数量，从而获得所述计数（22）。超过计数阈值（21）的计数被定义为可靠计数，计数低于或等于计数阈值的计数被定义为不可靠计数。对于外插函数中的第一个参数，使用较低和较高的值计算两个不可靠的计数。如果两个不可靠计数的差异小于或等于计数差（e），则第一个参数被认为等同于较低的值。本发明还公开了一种相应的尾部外推器。

4. 发明申请

WO2002091283A1 METHOD AND APPARATUS FOR COMPENSATING FOR TIMING VARIANCES IN DIGITAL DATA TRANSMISSION CHANNELS 审中-公开
标题翻译：用于补偿数字数据传输通道中的时序变量的方法和装置
公开(公告)号：WO2002091283A1
公开(公告)日：2002-11-14
申请号：PCT/US2002/013936
申请日：2002-05-03
申请人： COREOPTICS, INC.
发明人： DORSCHKY, Claus , KUPFER, Theodor , PRESSLEIN, Paul
IPC分类号： G06K5/04
CPC分类号： G06F1/04
摘要： A high-speed digital interface circuit for use with an N bit digital data signal is disclosed. The circuit comprises a source device (12) that initially receives the N bit digital data signal, and a sink device (14) that receives the N bit digital data signal from the source device (12). The N bit digital date signal has a skew when received by the sink device (14). A detection circuit in the sink device (14) detects the skew in the N bit digital data signal and generates a skew detection signal. A line (28) supplies the skew detection signal to the source device (12). A compensation circuit in the source device (12) receives the skew detection signal and compensates for the skew in the N bit digital data signal.
摘要翻译：公开了一种与N位数字数据信号一起使用的高速数字接口电路。电路包括初始接收N位数字数据信号的源设备（12）和从源设备（12）接收N位数字数据信号的宿设备（14）。当由宿设备（14）接收时，N位数字日期信号具有偏斜。宿设备（14）中的检测电路检测N位数字数据信号中的偏斜，并产生偏斜检测信号。线（28）将偏斜检测信号提供给源装置（12）。源装置（12）中的补偿电路接收偏斜检测信号并补偿N位数字数据信号中的偏斜。

5. 发明申请

WO2011010259A3 CLOCK RECOVERY FOR OPTICAL TRANSMISSION SYSTEMS 审中-公开
标题翻译：时分复用光传输系统
公开(公告)号：WO2011010259A3
公开(公告)日：2011-04-07
申请号：PCT/IB2010053252
申请日：2010-07-16
申请人： COREOPTICS INC , FLUDGER CHRISTOPHER
发明人： FLUDGER CHRISTOPHER
IPC分类号： H04B10/61
CPC分类号： H04B10/6165 , H04B10/61 , H04B10/611 , H04B10/614 , H04L25/03057
摘要： A receiver for an optical communications system which corrects distortion of a received signal. A clock recovery system utilising a feedback and feedforward system are provided. The feedback loop comprises a phase detector and a clock source, while the feedforward loop comprises the phase detector and a delay element for delaying the output of distortion correction system. The feedback loop has a significantly lower bandwidth than the feedforward path. There are also provided methods of optimising tap weights and of acquiring initial tap weights.
摘要翻译：用于校正接收信号失真的光通信系统的接收器。提供了一种利用反馈和前馈系统的时钟恢复系统。反馈回路包括相位检测器和时钟源，而前馈回路包括相位检测器和用于延迟失真校正系统的输出的延迟元件。反馈回路具有比前馈路径低得多的带宽。还提供了优化抽头权重和获取初始抽头权重的方法。

6. 发明申请

WO2010130595A1 SWAP TOLERANT CODING AND DECODING CIRCUITS AND METHODS 审中-公开
标题翻译： SWAP容限编码和解码电路及方法
公开(公告)号：WO2010130595A1
公开(公告)日：2010-11-18
申请号：PCT/EP2010/055978
申请日：2010-05-03
申请人： COREOPTICS INC. , BELLINGRATH, Thomas
发明人： BELLINGRATH, Thomas
IPC分类号： H04L25/49 , H04L27/20
CPC分类号： H04L25/4906 , H04L27/2071
摘要： This invention relates to a coding circuit for generating a swap tolerant code. The coding circuit comprises a first and second input (540, 541 ), an odd parity pair detector (535), a memory (533), and an output circuit (536, 537, 551; 736, 737, 751 ). Each of the first and second inputs (540, 541 ) receive a stream of serial data. The odd parity pair detector (535) outputs an odd parity pair signal if the bits received at said first and second inputs (540, 541 ) have different logical values and therefore constitute an odd parity pair. The memory (533) stores information on a previous odd parity pair. The output circuit outputs the previous odd parity pair, if said first input (540) provides a logical 1 and said second input (541 ) provides a logical 0. The output circuit outputs the inverted previous odd parity pair, if said first input (540) provides a logical 0 and said second input (541 ) provides a logical 1. The invention further provides a corresponding decoding circuit, and coding and decoding methods. Further the invention relates to a coding circuit for inversion tolerant coding, a corresponding decoding circuit and coding and decoding methods.
摘要翻译：本发明涉及一种用于生成交换容错码的编码电路。编码电路包括第一和第二输入（540,541），奇校验对检测器（535），存储器（533）和输出电路（536,537,551; 736,737,751）。第一和第二输入（540,541）中的每一个接收串行数据流。如果在所述第一和第二输入（540,541）处接收的比特具有不同的逻辑值并且因此构成奇偶校验对，则奇校验对检测器（535）输出奇校验对信号。存储器（533）存储关于先前的奇校验对的信息。如果所述第一输入（540）提供逻辑1，并且所述第二输入（541）提供逻辑0，则输出电路输出先前的奇偶校验对。如果所述第一输入（540））提供逻辑0，并且所述第二输入（541）提供逻辑1.本发明还提供相应的解码电路，以及编码和解码方法。此外，本发明涉及一种用于反转容限编码的编码电路，一种对应的解码电路和编码和解码方法。

7. 发明申请

WO2005011220A1 CHANNEL ESTIMATION AND SEQUENCE ESTIMATION FOR THE RECEPTION OF OPTICAL SIGNAL 审中-公开
标题翻译：用于接收光信号的信道估计和序列估计
公开(公告)号：WO2005011220A1
公开(公告)日：2005-02-03
申请号：PCT/EP2004/007155
申请日：2004-07-01
申请人： COREOPTICS INC. , LANGENBACH, Stefan , STOJANOVIC, Nebojsa
发明人： LANGENBACH, Stefan , STOJANOVIC, Nebojsa
IPC分类号： H04L25/03
CPC分类号： H04L25/03197 , H04L7/0004 , H04L7/007
摘要： The application relates to channel estimation. The method comprises digitizing an analogue signal representing a sequence of symbols thereby associating one digital word with the level of said analogue signal at each sampling time. The most likely sequence of symbols is detected. To this end branch metrics are provided. According to one embodiment, a symbol period comprises at least two sampling times. Moreover the branch metrics are obtained from frequencies of digital words resulting from a digitizing and the symbols of the most likely sequence. According to another embodiment a symbol period comprises at least one sampling time. Events are counted wherein each event is defined by a channel state and a current digital word. Each channel state is defined by a pattern of symbols relative to a current symbol determined at the time of a current digital word. A model distribution is fitted to event counts and a branch metrics is obtained from the fitted model distribution. Moreover the invention relates to corresponding symbol detectors for optical receivers.
摘要翻译：该应用涉及信道估计。该方法包括数字化表示符号序列的模拟信号，从而在每个采样时间将一个数字字与所述模拟信号的电平相关联。检测到最可能的符号序列。为此，提供了分支指标。根据一个实施例，符号周期包括至少两个采样时间。此外，分支度量是从数字化产生的数字字的频率和最可能的序列的符号获得的。根据另一实施例，符号周期包括至少一个采样时间。计数事件，其中每个事件由信道状态和当前数字字定义。每个信道状态由相对于当前数字字时确定的当前符号的符号模式来定义。模型分布适用于事件计数，并从拟合模型分布获得分支度量。此外，本发明涉及用于光接收机的相应符号检测器。

8. 发明申请

WO2009109582A1 PHASE CONTROL CIRCUIT AND METHOD FOR OPTICAL RECEIVERS 审中-公开
标题翻译：光接收机的相位控制电路和方法
公开(公告)号：WO2009109582A1
公开(公告)日：2009-09-11
申请号：PCT/EP2009/052515
申请日：2009-03-03
申请人： COREOPTICS INC. , FLUDGER, Christopher
发明人： FLUDGER, Christopher
IPC分类号： H04L27/22 , H04B10/158
CPC分类号： H04L27/223 , H04B10/677
摘要： This invention relates to a phase control circuit for an optical receiver (1). The phase control circuit (9, 19) comprises a non-linear element (22) and a power detector (24). The non-linear element (22) has a rectifying characteristic, inputs the received electrical signal (7, 17) and provides a rectified signal at its output. The power detector (24) provides an error signal which is used to obtain a phase control signal (5) which is output by the phase control circuit. The invention further relates to a corresponding method for phase control of an optical receiver (1).
摘要翻译：本发明涉及一种用于光接收器（1）的相位控制电路。相位控制电路（9,19）包括非线性元件（22）和功率检测器（24）。非线性元件（22）具有整流特性，输入接收的电信号（7,17），并在其输出端提供整流信号。功率检测器（24）提供用于获得由相位控制电路输出的相位控制信号（5）的误差信号。本发明还涉及一种用于光接收器（1）的相位控制的相应方法。

9. 发明申请

WO2005011220A8 CHANNEL ESTIMATION AND SEQUENCE ESTIMATION FOR THE RECEPTION OF OPTICAL SIGNAL 审中-公开
标题翻译：光信号接收的信道估计和序列估计
公开(公告)号：WO2005011220A8
公开(公告)日：2005-03-24
申请号：PCT/EP2004007155
申请日：2004-07-01
申请人： LANGENBACH STEFAN , STOJANOVIC NEBOJSA , COREOPTICS INC
发明人： LANGENBACH STEFAN , STOJANOVIC NEBOJSA
IPC分类号： H04L25/03
CPC分类号： H04L25/03197 , H04L7/0004 , H04L7/007
摘要： The application relates to channel estimation. The method comprises digitizing an analogue signal representing a sequence of symbols thereby associating one digital word with the level of said analogue signal at each sampling time. The most likely sequence of symbols is detected. To this end branch metrics are provided. According to one embodiment, a symbol period comprises at least two sampling times. Moreover the branch metrics are obtained from frequencies of digital words resulting from a digitizing and the symbols of the most likely sequence. According to another embodiment a symbol period comprises at least one sampling time. Events are counted wherein each event is defined by a channel state and a current digital word. Each channel state is defined by a pattern of symbols relative to a current symbol determined at the time of a current digital word. A model distribution is fitted to event counts and a branch metrics is obtained from the fitted model distribution. Moreover the invention relates to corresponding symbol detectors for optical receivers.
摘要翻译：该应用涉及信道估计。该方法包括数字化表示一系列符号的模拟信号，由此在每个采样时间将一个数字字与所述模拟信号的电平相关联。检测到最可能的符号序列。为此提供了分支指标。根据一个实施例，符号周期包括至少两个采样时间。此外，分支度量是从数字化产生的数字字的频率和最可能的序列的符号中获得的。根据另一个实施例，符号周期包括至少一个采样时间。事件被计数，其中每个事件由信道状态和当前数字字定义。每个信道状态由相对于当前数字字时确定的当前符号的符号模式定义。模型分布符合事件计数，分支度量从拟合模型分布中获得。此外，本发明涉及用于光接收机的对应符号检测器。

10. 发明申请

WO2004098051A1 METHOD AND CIRCUIT FOR CONTROLLING AMPLIFICATION 审中-公开
标题翻译：用于控制放大的方法和电路
公开(公告)号：WO2004098051A1
公开(公告)日：2004-11-11
申请号：PCT/EP2004/004337
申请日：2004-04-23
申请人： COREOPTICS INC. , LANGENBACH, Stefan , STOJANOVIC, Nebojsa
发明人： LANGENBACH, Stefan , STOJANOVIC, Nebojsa
IPC分类号： H03G3/30
CPC分类号： H03G3/3078 , H03G3/001 , H03G3/3052 , H03G3/3068 , H03M1/185
摘要： This invention relates to a method for controlling an amplification within a receiver. The gain of a variable gain amplifier which amplifies an input signal to obtain a gain-controlled signal is set. Said gain controlled signal is analog-to-digital converted. Thereby digital words are generated. Each digital word has a value out of a plurality of possible digital values. Digital words having a value within a first and a second subset of the possible digital values are counted in order to generate a first and a second counter value. The gain is set in accordance with the first and second counter values in a fashion that all counter values are as equal as possible. Furthermore, this invention is related to a circuit to be used within a receiver for adjusting the gain of a variable gain amplifier in order to ensure a proper analog-to-digital conversion.
摘要翻译：本发明涉及一种用于控制接收机内的放大的方法。设置放大输入信号以获得增益控制信号的可变增益放大器的增益。所述增益控制信号被模数转换。从而产生数字字。每个数字字都具有多个可能的数字值中的值。对具有可能的数字值的第一和第二子集内的值的数字字进行计数，以产生第一和第二计数器值。按照所有计数器值尽可能相等的方式，根据第一和第二计数器值设置增益。此外，本发明涉及用于调节可变增益放大器的增益的接收机内使用的电路，以便确保适当的模数转换。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式