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1. 发明申请

WO2011041330A1 TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT 审中-公开
标题翻译：并行处理单元的TRAP操作架构
公开(公告)号：WO2011041330A1
公开(公告)日：2011-04-07
申请号：PCT/US2010/050592
申请日：2010-09-28
申请人： NVIDIA CORPORATION , SHEBANOW, Michael, C. , CHOQUETTE, Jack , COON, Brett, W. , HEINRICH, Steven, J. , KALAIAH, Aravind , NICKOLLS, John, R. , SALINAS, Daniel , SIU, Ming , THORN, Tommy , WANG, Nicholas
发明人： SHEBANOW, Michael, C. , CHOQUETTE, Jack , COON, Brett, W. , HEINRICH, Steven, J. , KALAIAH, Aravind , NICKOLLS, John, R. , SALINAS, Daniel , SIU, Ming , THORN, Tommy , WANG, Nicholas
IPC分类号： G06F7/38
CPC分类号： G06F9/327 , G06F9/3851 , G06F9/3861
摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.
摘要翻译：陷阱处理器架构被并入到诸如GPU的并行处理子系统中。陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

2. 发明申请

WO2011038257A1 UNIFIED ADDRESSING AND INSTRUCTIONS FOR ACCESSING PARALLEL MEMORY SPACES 审中-公开
标题翻译：用于访问并行存储空间的统一寻址和指令
公开(公告)号：WO2011038257A1
公开(公告)日：2011-03-31
申请号：PCT/US2010/050240
申请日：2010-09-24
申请人： NVIDIA CORPORATION , NICKOLLS, John, R. , COON, Brett, W. , BUCK, Ian, A. , GLANVILLE, Robert, Steven
发明人： NICKOLLS, John, R. , COON, Brett, W. , BUCK, Ian, A. , GLANVILLE, Robert, Steven
IPC分类号： G06F15/167
CPC分类号： G06F12/1054 , G06F12/0284 , G06F12/109 , G06F13/404 , G06F2212/302 , G06F2212/656
摘要： One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.
摘要翻译：本发明的一个实施例提出了一种用于将多个不同的并行存储器空间的寻址统一为用于线程的单个地址空间的技术。统一的存储空间地址被转换为访问该线程的并行存储器空间之一的地址。可以使用单一类型的加载或存储指令，其指定线程的统一存储器空间地址，而不是使用不同类型的加载或存储指令来访问每个不同的并行存储器空间。

3. 发明申请

WO2011038253A1 CONFIGURABLE CACHE FOR MULTIPLE CLIENTS 审中-公开
标题翻译：多个客户端的可配置缓存
公开(公告)号：WO2011038253A1
公开(公告)日：2011-03-31
申请号：PCT/US2010/050233
申请日：2010-09-24
申请人： NVIDIA CORPORATION , MINKIN, Alexander L. , HEINRICH, Steven James , SELVANESAN, RaJeshwaran , COON, Brett W. , MCCARVER, Charles , RAJENDRAN, Anjana , CARLTON, Stewart G.
发明人： MINKIN, Alexander L. , HEINRICH, Steven James , SELVANESAN, RaJeshwaran , COON, Brett W. , MCCARVER, Charles , RAJENDRAN, Anjana , CARLTON, Stewart G.
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F2212/2515 , G06F2212/301 , G06F2212/6012
摘要： One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A "direct mapped" storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A "local and global cache" storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.
摘要翻译：本发明的一个实施例提出了一种用于提供作为中央存储资源的L1高速缓存的技术。 L1缓存为多个客户端提供不同的延迟和带宽要求。可以重新配置L1高速缓存以创建多个存储空间，使得L1高速缓存可以替代先前架构中的专用缓冲器，高速缓存和FIFO。配置在L1高速缓存内的“直接映射”存储区可以替代专用缓冲器，FIFO和接口路径，允许L1高速缓存的客户端交换属性和原始数据。直接映射存储区域可以用作全局寄存器文件。配置在L1高速缓存内的“本地和全局高速缓存”存储区域可用于支持对多个空间的加载/存储存储器请求。这些空格包括全局，本地和回调栈（CRS）内存。

4. 发明申请

WO2011038106A1 INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY 审中-公开
标题翻译：用于管理并行缓存高速缓存的指令
公开(公告)号：WO2011038106A1
公开(公告)日：2011-03-31
申请号：PCT/US2010/049978
申请日：2010-09-23
申请人： NVIDIA CORPORATION , NICKOLLS, John, R. , COON, Brett, W. , SHEBANOW, Michael, C.
发明人： NICKOLLS, John, R. , COON, Brett, W. , SHEBANOW, Michael, C.
IPC分类号： G06F9/30
CPC分类号： G06F9/3887 , G06F9/30043 , G06F9/3009 , G06F9/3836 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/121 , G06F2212/452
摘要： A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.
摘要翻译：一种用于在处理单元中管理并行高速缓存层级的方法。该方法包括从调度器单元接收指令，其中指令包括加载指令或存储指令; 确定所述指令包括高速缓存操作修饰符，所述高速缓存操作修饰符标识用于在所述并行高速缓存层级的一个或多个级别缓存与所述指令相关联的数据并且基于高速缓存操作修饰符执行指令并缓存与指令相关联的数据。

5. 发明申请

WO2005093665A1 REGISTER BASED QUEUING FOR TEXTURE REQUESTS 审中-公开
标题翻译：基于注册码的纹身要求
公开(公告)号：WO2005093665A1
公开(公告)日：2005-10-06
申请号：PCT/US2005/003999
申请日：2005-02-09
申请人： NVIDIA CORPORATION , LINDHOLM, John, Erik , NICKOLLS, John, R. , MOY, Simon, S. , COON, Brett, W.
发明人： LINDHOLM, John, Erik , NICKOLLS, John, R. , MOY, Simon, S. , COON, Brett, W.
IPC分类号： G06T15/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

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