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1. 发明申请

WO2002082278A1 CACHE WRITE BYPASS SYSTEM 审中-公开
标题翻译：高速缓存写入旁路系统
公开(公告)号：WO2002082278A1
公开(公告)日：2002-10-17
申请号：PCT/US2002/006682
申请日：2002-03-05
申请人： CLEARWATER NETWORKS, INC.
发明人： NEMIROVSKY, Mario , MELVIN, Stephen
IPC分类号： G06F12/08
CPC分类号： G06F9/546 , G06F12/0853 , G06F12/0855 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A bypass system (2901) for a data cache (1002) has two ports to the data cache, registers for multiple data entries (2902), a bus connection for accepting read and write operations to the cache, and address matching and switching logic (2903). The system is characterized in that write operations that hit in the data cache are stored as elements in the bypass structure before the data is written to the data cache, and read operations use the address matching logic to search the elements of the bypass structure to identify and use any one or more of the entries representing data more recent than that stored in the data cache memory array, such that a subsequent write operation may free a memory port for a write stored in the bypass structure to be written to the data cache memory array. In a preferred embodiment there are six entries in the bypass system, and stalls are eliminated.
摘要翻译：用于数据高速缓存（1002）的旁路系统（2901）具有到数据高速缓存的两个端口，用于多个数据条目（2902）的寄存器，用于接受对高速缓存的读和写操作的总线连接以及地址匹配和切换逻辑（ 2903）。该系统的特征在于，在将数据写入数据高速缓存之前，在数据高速缓冲存储器中的写入操作作为元件存储在旁路结构中，并且读取操作使用地址匹配逻辑来搜索旁路结构的元件以识别并且使用表示比存储在数据高速缓冲存储器阵列中的数据更新的任何一个或多个条目，使得随后的写入操作可以释放存储在旁路结构中的写入的存储器端口被写入数据高速缓存存储器阵列。在优选实施例中，在旁路系统中有六个条目，并且消除了档位。

2. 发明申请

WO2003023556A2 EXTENDED INSTRUCTION SET FOR PACKET PROCESSING APPLICATIONS 审中-公开
标题翻译：分组处理应用的扩展指令集
公开(公告)号：WO2003023556A2
公开(公告)日：2003-03-20
申请号：PCT/US2002/026474
申请日：2002-08-19
申请人： CLEARWATER NETWORKS, INC.
发明人： MUSOLL, Enrique , NEMIROVSKY, Mario , MELVIN, Stephen
IPC分类号： G06F
CPC分类号： G06F9/30003 , G06F9/30101 , G06F9/3851 , G06F9/3885 , G06F9/5016 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.
摘要翻译：公开了用于动态多流处理器的软件程序扩展。该扩展包括实现分组管理组件和处理器的核心处理组件之间的协调交互的指令集。该软件程序包括用于管理分组上载和下载到存储器和从存储器下载的一部分，其一部分用于管理与入队和出队数据分组相关联的特定存储器分配和解除分配，其一部分用于管理多个上下文的使用专用于处理单个数据包; 及其一部分，用于管理与数据包处理相关联的算术和其他上下文存储器功能的选择和利用。该扩展补充了标准数据包处理程序体系结构，用于具有独立于流式处理器单元运行的数据包管理单元的处理器。

3. 发明申请

WO03005645A2 METHOD AND APPARATUS FOR NON-SPECULATIVE PRE-FETCH OPERATION IN DATA PACKET PROCESSING 审中-公开
标题翻译：数据分组处理中非调制型预充电操作的方法和装置
公开(公告)号：WO03005645A2
公开(公告)日：2003-01-16
申请号：PCT/US0220316
申请日：2002-06-25
申请人： CLEARWATER NETWORKS INC
发明人： SAMPATH NANDAKUMAR , MUSOLL ENRIQUE , MELVIN STEPHEN , NEMIROVSKY MARIO
IPC分类号： G06F15/177 , G06F9/46 , H04L12/56 , H04L12/28
CPC分类号： H04L49/9073 , G06F9/546 , H04L45/00 , H04L45/56 , H04L45/60 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/10 , H04L49/20 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/30 , H04L49/3036 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L69/12
摘要： A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and en-queuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
摘要翻译：提供了一种系统，用于使得能够在分组处理器的即时分组处理之前的后台执行用于处理指令的非推测性预取操作。该系统包括：数据包管理单元，用于接收数据分组并进行处理，用于处理数据分组的处理器单元，用于保存上下文寄存器的处理器核心存储器和用于处理的功能单元;存储器，用于保存多个指令线程和可配置的硬件表，用于将队列与指向开始指令线程的指针相关联。分组管理单元在处理器核心中选择用于处理数据分组的可用上下文，参考表格，并将指针传送到处理器，使得处理器能够对指令进行非推测性预取。

4. 发明申请

WO2002103528A1 METHOD AND APPARATUS FOR ALLOCATING AND DE-ALLOCATING CONSECUTIVE BLOCKS OF MEMORY IN BACKGROUND MEMORY MANAGEMENT 审中-公开
标题翻译：在背景记忆管理中分配和分配存储器的相关块的方法和装置
公开(公告)号：WO2002103528A1
公开(公告)日：2002-12-27
申请号：PCT/US2002/012474
申请日：2002-04-18
申请人： CLEARWATER NETWORKS, INC.
发明人： MUSOLL, Enrique , NEMIROVSKY, Mario
IPC分类号： G06F12/02
CPC分类号： H04L49/9047 , G06F12/023 , H04L49/90 , H04L49/901
摘要： A system (300) for allocating storage of incoming data packets into a memory (102) of a packet processor (100). The data packets are mapped to blocks of fixed byte sizes.
摘要翻译：一种用于将输入数据分组的存储分配到分组处理器（100）的存储器（102）中的系统（300）。数据包被映射到固定字节大小的块。

5. 发明申请

WO2002102001A1 METHOD AND APPARATUS FOR OPTIMIZING SELECTION OF AVAILABLE CONTEXTS FOR PACKET PROCESSING IN MULTI-STREAM PACKET PROCESSING 审中-公开
标题翻译：用于优化选择可用于在多流包分组处理中进行分组处理的内容的方法和装置
公开(公告)号：WO2002102001A1
公开(公告)日：2002-12-19
申请号：PCT/US2002/012469
申请日：2002-04-18
申请人： CLEARWATER NETWORKS, INC.
发明人： MUSOLL, Enrique , NEMIROVSKY, Mario
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L69/12 , H04L69/22
摘要： A context-selection mechanism (201) is provided for selecting a best context from a pool of contexts (229) for processing a data packet. The context selection mechanism (201) comprises, an interface (203) for communicating with a multi-streaming processor (105); circuitry for computing input data into a result value according to logic rule and for selecting a context based on the computed value and a loading mechanism (219) for preloading the packet information into the selected context for subsequent processing. The computation of the input data functions to enable identification and selection of a best context for processing a data packet according to the logic rule at the instant time such that a multitude of subsequent context selections over a period of time acts to balance load pressure on functional units housed within the multi-streaming processor (105) and required for packet processing. In preferred aspects, programmable singular or multiple predictive rules of logic are utulized in the selection process.
摘要翻译：提供上下文选择机制（201），用于从用于处理数据分组的上下文池（229）中选择最佳上下文。上下文选择机制（201）包括：与多流处理器（105）通信的接口（203）; 用于根据逻辑规则将输入数据计算到结果值中并且用于基于所计算的值来选择上下文的电路和用于将分组信息预加载到所选择的上下文中用于后续处理的加载机制（219）。输入数据的计算功能用于根据逻辑规则来识别和选择用于处理数据分组的最佳上下文，使得在一段时间内多个随后的上下文选择用于平衡负载压力对功能性容纳在多流处理器（105）内并且分组处理所需的单元。在优选的方面，逻辑的可编程奇异或多重预测规则在选择过程中被排除。

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