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1. 发明申请

WO2009120479A3 OFF-LINE TASK LIST ARCHITECTURE 审中-公开
标题翻译：离线任务列表架构
公开(公告)号：WO2009120479A3
公开(公告)日：2010-01-14
申请号：PCT/US2009036437
申请日：2009-03-07
申请人： QUALCOMM INC , CHAUDHURI ARUNAVA , YAO IWEN , LIN JEREMY H , GURSKI REMI , YEN KEVIN W
发明人： CHAUDHURI ARUNAVA , YAO IWEN , LIN JEREMY H , GURSKI REMI , YEN KEVIN W
IPC分类号： G06F15/78 , G06F9/30 , G06F9/38 , G06F9/48 , H04M1/725
CPC分类号： G06F9/3879 , G06F15/7814
摘要： A flexible and reconf?gurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub- circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub- circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重构的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合的存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路任务管理器从其任务列表中读取任务指令，并根据指令控制其相关的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

2. 发明申请

WO2009142804A2 BROADBAND PILOT CHANNEL ESTIMATION USING A REDUCED ORDER FFT AND A HARDWARE INTERPOLATOR 审中-公开
标题翻译：使用减少订单FFT和硬件插入器的宽带导频信道估计
公开(公告)号：WO2009142804A2
公开(公告)日：2009-11-26
申请号：PCT/US2009037438
申请日：2009-03-17
申请人： QUALCOMM INC , BUDIANU PETRU CRISTIAN , CHAUDHURI ARUNAVA , CHALLA RAGHU N
发明人： BUDIANU PETRU CRISTIAN , CHAUDHURI ARUNAVA , CHALLA RAGHU N
IPC分类号： H04J11/00 , H04K1/10
CPC分类号： H04L25/0202 , H04B1/76 , H04J11/00 , H04L25/0212 , H04L25/023 , H04L25/0232
摘要： Within a receiver, a channel estimation mechanism involves a hardware interpolator. In a first mode, narrowband pilot values are analyzed to generate channel parameters that are supplied to the interpolator such that the interpolator generates channel estimate values. The channel estimate values are used to demodulate a tile of a frame. In a second mode, broadband pilot values are supplied to an IFFT, thereby generating time domain values. After time domain processing, an FFT is employed to generate intermediate channel estimate values. These intermediate values are analyzed to determine channel parameters, which in turn are supplied to the hardware interpolator so that the interpolator generates a larger number of channel estimate values. After phase adjustment, the channel estimate values are used in demodulation. Use of the interpolator in the broadband mode allows the FFT employed to be of a smaller order, and to consume less power and/or processing resources.
摘要翻译：在接收机内，信道估计机制涉及硬件插值器。在第一模式中，分析窄带导频值以产生提供给内插器的信道参数，使得内插器生成信道估计值。信道估计值用于解调帧的瓦片。在第二模式中，宽带导频值被提供给IFFT，从而产生时域值。在时域处理之后，采用FFT来产生中间信道估计值。分析这些中间值以确定信道参数，其又被提供给硬件插值器，使得内插器产生更大数量的信道估计值。相位调整后，信道估计值用于解调。在宽带模式下使用内插器允许所采用的FFT具有较小的次序，并且消耗更少的功率和/或处理资源。

3. 发明申请

WO2005036845A1 FREQUENCY ERROR ESTIMATION USING MULTIPLE INTEGRATION LENGTHS 审中-公开
标题翻译：使用多重整合长度的频率误差估计
公开(公告)号：WO2005036845A1
公开(公告)日：2005-04-21
申请号：PCT/US2004/033114
申请日：2004-10-07
申请人： QUALCOMM INCORPORATED , RICK, Roland, R. , CHAUDHURI, Arunava
发明人： RICK, Roland, R. , CHAUDHURI, Arunava
IPC分类号： H04L27/00
CPC分类号： H04L27/0014 , H04L2027/0046 , H04L2027/0065 , H04L2027/0081
摘要： A wireless communication device (WCD) estimates frequency error by averaging frequency error estimates over multiple integration lengths to generate short-term and long-term averages. The WCD compares the short-term and long-term averages with short-term and long-term thresholds. The long-term thresholds are lower than the short-term threshold. If the average for any integration length exceeds its respective threshold, a frequency offset is determined and an oscillator frequency is adjusted based on that frequency offset. The use of both short-term and long-term thresholds facilitates responding quickly to relatively large changes in the frequency error, while ignoring smaller changes that may be indicative of noise in the system rather than actual changes in the frequency error.
摘要翻译：无线通信设备（WCD）通过在多个积分长度上平均频率误差估计来估计频率误差，以产生短期和长期平均值。世界水坝委员会将短期和长期平均值与短期和长期门槛进行比较。长期门槛低于短期门槛。如果任何积分长度的平均值超过其各自的阈值，则确定频率偏移，并且基于该频率偏移来调整振荡器频率。使用短期和长期阈值有助于快速响应频率误差相对较大的变化，同时忽略可能表示系统噪声的较小变化，而不是频率误差的实际变化。

4. 发明申请

WO2009123838A2 EFFICIENT PARALLEL SUB-PACKET DECODING USING MULTIPLE DECODERS 审中-公开
标题翻译：使用多个解码器的高效并行子包解码
公开(公告)号：WO2009123838A2
公开(公告)日：2009-10-08
申请号：PCT/US2009/036709
申请日：2009-03-10
申请人： QUALCOMM INCORPORATED , ZANOTELLI, Joseph, V , NATH, Mrinal, M , CHAUDHURI, Arunava , GHOSH, Kaushik , CHALLA, Raghu, N. , JING, Weihong
发明人： ZANOTELLI, Joseph, V , NATH, Mrinal, M , CHAUDHURI, Arunava , GHOSH, Kaushik , CHALLA, Raghu, N. , JING, Weihong
IPC分类号： H04L1/00 , G06F9/38 , H03M13/29 , H04N7/26
CPC分类号： H04L1/0045 , H03M13/2957 , H03M13/41 , H03M13/6508 , H03M13/6561 , H04L1/0052
摘要： A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.
摘要翻译：接收机内的可配置解码器（例如，在无线通信设备内）包括许多解码器。在一种模式中，多个解码器用于解码分组的不同子分组。当一个解码器完成对分组给它的最后一个子分组的解码时，该解码器产生分组完成指示。控制电路接收分组完成指示，并且当所有解码器已经生成分组完成指示时，控制电路启动动作。在一个示例中，动作是处理器的中断。处理器通过从控制电路读取状态信息进行响应，从而复位中断。分组结束标记可用于生成分组完成指示并产生EOP中断。类似地，组尾标记可用于生成组完成指示并产生EOG中断。解码器块可配置为使用一个或多个解码器来处理分组的子分组。

5. 发明申请

WO2009120913A3 REUSE ENGINE WITH TASK LIST FOR FAST FOURIER TRANSFORM AND METHOD OF USING THE SAME 审中-公开
标题翻译：用快速傅里叶变换的任务列表重新使用发动机及其使用方法
公开(公告)号：WO2009120913A3
公开(公告)日：2011-01-13
申请号：PCT/US2009038473
申请日：2009-03-27
申请人： QUALCOMM INC , CHAUDHURI ARUNAVA , SAMPATH HEMANTH , YAO IWEN , LIN JEREMY H , CHALLA RAGHU N , WU MIN
发明人： CHAUDHURI ARUNAVA , SAMPATH HEMANTH , YAO IWEN , LIN JEREMY H , CHALLA RAGHU N , WU MIN
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L5/0007 , H04L5/0023 , H04L5/0053 , H04L27/265 , H04L27/2662
摘要： An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.
摘要翻译：用于执行傅里叶变换的改进的处理引擎包括配置成处理顺序指令软件命令的指令处理器和耦合到指令处理器的傅里叶变换引擎。傅立叶变换引擎被配置为对串行数据流执行傅里叶变换。傅里叶变换引擎被配置为经由一组软件任务从指令处理器接收配置信息和操作数据。

6. 发明申请

WO2009142815A3 SYSTEMS AND METHODS FOR SENDING AN ACKNOWLEDGMENT MESSAGE IN A WIRELESS COMMUNICATION SYSTEM 审中-公开
标题翻译：在无线通信系统中发送确认消息的系统和方法
公开(公告)号：WO2009142815A3
公开(公告)日：2010-04-29
申请号：PCT/US2009038209
申请日：2009-03-25
申请人： QUALCOMM INC , CHAUDHURI ARUNAVA , SAMPATH HEMANTH , CHALLA RAGHU N , PALANKI RAVI , KANDUKURI NARAYANA SUNIL KUMAR
发明人： CHAUDHURI ARUNAVA , SAMPATH HEMANTH , CHALLA RAGHU N , PALANKI RAVI , KANDUKURI NARAYANA SUNIL KUMAR
IPC分类号： H04L1/16
CPC分类号： H04L1/20 , H04L1/1607 , H04L1/208
摘要： A method for sending an acknowledgment message in a wireless communication system is disclosed. A first signal is received before receiving a second signal from a transmitter. Decoded first data is extracted from the first signal. A third signal is produced by encoding and modulating the decoded first data. The second signal is demodulated to produce second symbols. The third signal and the second symbols are correlated.
摘要翻译：公开了一种用于在无线通信系统中发送确认消息的方法。在从发射机接收第二信号之前接收第一信号。从第一信号中提取解码的第一数据。通过对解码的第一数据进行编码和调制来产生第三信号。第二信号被解调以产生第二符号。第三信号和第二符号相关。

7. 发明申请

WO2009120479A2 OFF-LINE TASK LIST ARCHITECTURE 审中-公开
标题翻译：离线任务列表架构
公开(公告)号：WO2009120479A2
公开(公告)日：2009-10-01
申请号：PCT/US2009/036437
申请日：2009-03-07
申请人： QUALCOMM INCORPORATED , CHAUDHURI, Arunava , YAO, Iwen , LIN, Jeremy, H. , GURSKI, Remi , YEN, Kevin, W.
发明人： CHAUDHURI, Arunava , YAO, Iwen , LIN, Jeremy, H. , GURSKI, Remi , YEN, Kevin, W.
IPC分类号： G06F15/78 , H04M1/725 , G06F9/48
CPC分类号： G06F9/3879 , G06F15/7814
摘要： A flexible and reconfϊgurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub- circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub- circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重构的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合的存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路任务管理器从其任务列表中读取任务指令，并根据指令控制其相关的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

8. 发明申请

WO2009123838A3 EFFICIENT PARALLEL SUB-PACKET DECODING USING MULTIPLE DECODERS, CONTROLLER AND TASK INSTRUCTIONS 审中-公开
标题翻译：使用多个解码器，控制器和任务指令的高效并行子包解码
公开(公告)号：WO2009123838A3
公开(公告)日：2009-12-10
申请号：PCT/US2009036709
申请日：2009-03-10
申请人： QUALCOMM INC , ZANOTELLI JOSEPH V , NATH MRINAL M , CHAUDHURI ARUNAVA , GHOSH KAUSHIK , CHALLA RAGHU N , JING WEIHONG
发明人： ZANOTELLI JOSEPH V , NATH MRINAL M , CHAUDHURI ARUNAVA , GHOSH KAUSHIK , CHALLA RAGHU N , JING WEIHONG
IPC分类号： H04L1/00 , G06F9/38 , H03M13/29 , H04N7/26
CPC分类号： H04L1/0045 , H03M13/2957 , H03M13/41 , H03M13/6508 , H03M13/6561 , H04L1/0052
摘要： A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.
摘要翻译：接收机内的可配置解码器（例如，在无线通信设备内）包括许多解码器。在一种模式中，多个解码器用于解码分组的不同子分组。当一个解码器完成对分组给它的最后一个子分组的解码时，该解码器产生分组完成指示。控制电路接收分组完成指示，并且当所有解码器已经生成分组完成指示时，控制电路启动动作。在一个示例中，动作是处理器的中断。处理器通过从控制电路读取状态信息进行响应，从而复位中断。分组结束标记可用于生成分组完成指示并产生EOP中断。类似地，组尾标记可用于生成组完成指示并产生EOG中断。解码器块可配置为使用一个或多个解码器来处理分组的子分组。

9. 发明申请

WO2009120480A1 RECONFIGURABLE WIRELESS MODEM SUB-CIRCUITS TO IMPLEMENT MULTIPLE AIR INTERFACE STANDARDS 审中-公开
标题翻译：可重构无线调制解调器子电路实现多个空中接口标准
公开(公告)号：WO2009120480A1
公开(公告)日：2009-10-01
申请号：PCT/US2009/036438
申请日：2009-03-07
申请人： QUALCOMM INCORPORATED , CHAUDHURI, Arunava , YAO, Iwen , LIN, Jeremy, H. , ROSTAMPISHEH, Ali , CHALLA, Raghu , SAMPATH, Hemanth , WU, Megan , ZANOTELLI, Joseph , NATH, Mrinal
发明人： CHAUDHURI, Arunava , YAO, Iwen , LIN, Jeremy, H. , ROSTAMPISHEH, Ali , CHALLA, Raghu , SAMPATH, Hemanth , WU, Megan , ZANOTELLI, Joseph , NATH, Mrinal
IPC分类号： G06F15/78 , H04M1/725
CPC分类号： G06F15/7842
摘要： A flexible and reconfϊgurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub- circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub- circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重构的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合的存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路任务管理器从其任务列表中读取任务指令，并根据指令控制其相关的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

10. 发明申请

WO2009120473A1 WALL CLOCK TIMER AND SYSTEM FOR GENERIC MODEM CONTROL 审中-公开
标题翻译：用于通用调制解调器控制的时钟定时器和系统
公开(公告)号：WO2009120473A1
公开(公告)日：2009-10-01
申请号：PCT/US2009/036248
申请日：2009-03-05
申请人： QUALCOMM INCORPORATED , CHAUDHURI, Arunava , YAO, Iwen , LIN, Jeremy, H. , GURSKI, Remi
发明人： CHAUDHURI, Arunava , YAO, Iwen , LIN, Jeremy, H. , GURSKI, Remi
IPC分类号： H04B1/40 , G06F13/24
CPC分类号： H04B1/406
摘要： A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.
摘要翻译：调制解调器（例如，蜂窝电话中的调制解调器）包括多个无线通信系统调制解调器子电路（WCSMSC）。每个WCSMSC接收由多个可编程定时器中相应的一个生成的控制信号。每个定时器从挂钟计数器接收相同的计数值序列。控制整个调制解调器操作的处理器可以编程定时器以在挂钟计数器的特定计数时间产生控制脉冲。处理器还可以编程定时器以产生周期性控制信号。当各种WCSMSC在帧的处理中开始运行时，从定时器输出的控制信号协调编排。通过定时器的可编程性，挂钟计时器系统可编程以产生定制的控制信号，使得具有任意帧结构的新协议和不同协议的帧可以由相同的调制解调器/定时器系统来处理。

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