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    • 4. 发明申请
    • CIRCUITRY TO DRIVE PARALLEL LOADS SEQUENTIALLY
    • 电路按顺序驱动并联负载
    • WO2013095769A1
    • 2013-06-27
    • PCT/US2012/061779
    • 2012-10-25
    • ALLEGRO MICROSYSTEMS, LLCLEE, Nai-ChiSZCZESZYNSKI, GregoryMANGTANI, Vijay
    • LEE, Nai-ChiSZCZESZYNSKI, GregoryMANGTANI, Vijay
    • H02M3/335H05B33/08
    • H05B33/0851H02M3/158H02M2001/0009H05B33/0818H05B33/0827Y02B20/346Y10T307/25
    • In one aspect, a circuit includes a plurality of comparators (50a, 50b, 50c). Each comparator is configured to receive a first input from a corresponding load of a plurality of loads (52a, 52b, 52c) and to receive a second input as a regulation voltage (Vreg). The circuit also Includes an amplifier (56) configured to receive signals provided by the plurality of comparators, a pulse-width modulation (PWM) circuit configured to receive a control signal from the amplifier and to provide a signal to a primary switch (42) to control voltage provided to the loads and an output switch sequencer (62) coupled to each of the comparators and configured to provide control signals (S1, S2, S3) to control switches (30a, 30b, 30c) coupled to the primary switch (42) enabling one control switch to be active at a time. Each control switch provides a voltage increase to a respective load of the plurality of loads if enabled.
    • 一方面,电路包括多个比较器(50a,50b,50c)。 每个比较器被配置为从多个负载(52a,52b,52c)的对应负载接收第一输入,并且接收作为调节电压(Vreg)的第二输入。 电路还包括被配置为接收由多个比较器提供的信号的放大器(56),配置成从放大器接收控制信号并向初级开关(42)提供信号的脉冲宽度调制(PWM)电路, 以控制提供给负载的电压以及耦合到每个比较器的输出开关定序器(62),并且被配置为提供控制信号(S1,S2,S3)以控制耦合到主开关的开关(30a,30b,30c) 42)一个控制开关一次有效。 如果启用,每个控制开关为多个负载的相应负载提供电压增加。
    • 7. 发明申请
    • AN INTRUSION DETECTION AND TRACKING SYSTEM
    • 入侵检测和跟踪系统
    • WO2012015688A2
    • 2012-02-02
    • PCT/US2011/044972
    • 2011-07-22
    • RAYTHEON COMPANYHABIB, Toni, S.HABIB, Wassim, S.LUNG, Teh-Kuang
    • HABIB, Toni, S.HABIB, Wassim, S.LUNG, Teh-Kuang
    • G08B13/24
    • G08B13/2491G01S5/0289
    • In one aspect, a method to detect an object in an area includes forming a wireless network among a plurality of nodes, each of the nodes being configured to generate an electromagnetic field (EMF) in the area and determining changes in the EMF between two nodes based on: a first difference in received signal strength values between a previously determined received signal strength value and a currently determined received signal strength value, a second difference in received signal strength values between the currently determined received signal strength value and an average received signal strength value and a third difference in link quality values between a previously determined link quality value and a currently determined link quality value. The method further comprises detecting the object based on the changes in the EMF.
    • 在一个方面,检测区域中的对象的方法包括在多个节点之间形成无线网络,每个节点被配置为在该区域中生成电磁场(EMF),并且 基于先前确定的接收信号强度值与当前确定的接收信号强度值之间的接收信号强度值的第一差异,确定当前确定的接收信号之间的接收信号强度值的第二差异,确定两个节点之间的EMF的变化 强度值和平均接收信号强度值以及先前确定的链路质量值与当前确定的链路质量值之间的链路质量值的第三差异。 该方法还包括基于EMF中的变化来检测对象。
    • 8. 发明申请
    • A WAVEFORM GENERATOR IN A MULTI-CHIP SYSTEM
    • 多芯片系统中的波形发生器
    • WO2011162923A1
    • 2011-12-29
    • PCT/US2011/038851
    • 2011-06-02
    • RAYTHEON COMPANYKATZ, David, J.REID, Stephen, R.
    • KATZ, David, J.REID, Stephen, R.
    • H04L7/033G06F1/02H04L25/14H03L7/081
    • G06F1/10H04L7/0338
    • In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit configured to provide a feedback signal to a driver IC. The IC system also includes the driver IC configured to receive a second clock signal and includes a waveform generator configured to provide synthesized waveforms from DC to K-band, a serializer/deserializer (SERDES) to receive data from the waveform generator and to provide the signal to the receiver IC and a phase selection circuit to provide a phase selection signal to the first integrated circuit based on the feedback signal. The phase selection signal calibrates the signal from the SERDES and provides phase correction to the SERDES.
    • 在一个方面,集成电路(IC)系统包括被配置为接收第一时钟信号并包括被配置为向驱动器IC提供反馈信号的反馈电路的接收器IC。 IC系统还包括被配置为接收第二时钟信号的驱动器IC,并且包括被配置为提供从DC到K波段的合成波形的波形发生器,用于从波形发生器接收数据的串行器/解串器(SERDES),并且提供 信号到接收器IC和相位选择电路,以基于反馈信号向第一集成电路提供相位选择信号。 相位选择信号校准来自SERDES的信号,并向SERDES提供相位校正。