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1. 发明申请

WO2014151986A1 SYNCHRONOUS MIRRORING IN NON-VOLATILE MEMORY SYSTEMS 审中-公开
标题翻译：非易失性存储器系统中的同步镜像
公开(公告)号：WO2014151986A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/026773
申请日：2014-03-13
申请人： VIRIDENT SYSTEMS INC.
发明人： KARAMCHETI, Vijay , MONDAL, Shibabrata , GOWDA, Swamy
IPC分类号： G06F12/02
CPC分类号： G06F11/2058 , G06F11/14 , G06F11/1451 , G06F11/2082 , G06F12/0246 , G06F2201/84 , G06F2212/7201 , G06F2212/7202
摘要： First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.
摘要翻译：接收第一数据以存储在第一非对称存储器件中。第一个写入阶段被识别为当前写入阶段。包括在第一非对称存储器件中的第一段被识别为可用于写入数据的下一段。第一个数据被写入第一个数据段。存储与第一段相关联的信息，以及指示第一段被写入第一写入阶段的信息。接收第二数据以存储在非对称存储器中。包括在第一非对称存储器件中的第二段被识别为可用于写入数据的下一段。第二个数据被写入第二个数据段。与第二段和第二存储块相关联的信息与指示第二段被写入第二写入阶段的信息一起被存储。

2. 发明申请

WO2009102821A3 METHODS AND APPARATUS FOR TWO-DIMENSIONAL MAIN MEMORY 审中-公开
标题翻译：二维主要记忆的方法和装置
公开(公告)号：WO2009102821A3
公开(公告)日：2009-12-17
申请号：PCT/US2009033843
申请日：2009-02-11
申请人： VIRIDENT SYSTEMS INC
发明人： KARAMCHETI VIJAY , GANAPATHY KUMAR
IPC分类号： G06F12/00 , G06F9/34 , G11C5/14 , G11C7/00
CPC分类号： G11C16/0408 , G06F7/78 , G06F12/0207 , G06F12/0246 , G06F12/0607 , G06F17/30477 , G06F2212/7201 , G06F2212/7208 , G11C16/06 , Y02D10/13
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

3. 发明申请

WO2009079478A1 DISTRIBUTING METADATA ACROSS MULTIPLE DIFFERENT DISRUPTION REGIONS WITHIN AN ASYMMETRIC MEMORY SYSTEM 审中-公开
标题翻译：在非对称存储器系统中分布多个不同的不同区域的元数据
公开(公告)号：WO2009079478A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/086887
申请日：2008-12-15
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , SINGHAI, Ashish
发明人： KARAMCHETI, Vijay , SINGHAI, Ashish
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F2212/1032 , G06F2212/7207 , G06F2212/7208
摘要： Metadata that corresponds to application data is distributed across different disruption regions of an asymmetric memory component such that metadata is written in the same disruption region as the application data to which it corresponds. A first block of application data is written to a first disruption region and a second block of application data is written to a second disruption region. A first block of metadata corresponding to the first block of application data and a second block of metadata corresponding to the second block of application data both are generated. The first block of metadata is written to the first disruption region and the second block of metadata is written to the second disruption region such that the first and second blocks of metadata are written to the same disruption regions as the blocks of application data to which they correspond.
摘要翻译：对应于应用数据的元数据分布在非对称存储器组件的不同中断区域上，使得元数据被写入与其对应的应用数据相同的中断区域。应用数据的第一块被写入第一中断区域，并且第二应用数据块被写入第二中断区域。生成对应于第一应用数据块的元数据的第一块和对应于第二应用数据块的第二元数据块。元数据的第一块被写入第一中断区域，并且第二块元数据被写入第二中断区域，使得第一和第二元数据块被写入到与它们的应用数据块相同的中断区域对应。

4. 发明申请

WO2008055271A3 SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY 审中-公开
标题翻译：无缝应用访问混合主内存
公开(公告)号：WO2008055271A3
公开(公告)日：2008-07-03
申请号：PCT/US2007083669
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS INC , KARAMCHETI VIJAY , OKIN KENNETH A , GANAPATHY KUMAR , SINGHAI ASHISH , PAREKH RAJESH
发明人： KARAMCHETI VIJAY , OKIN KENNETH A , GANAPATHY KUMAR , SINGHAI ASHISH , PAREKH RAJESH
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02B60/1225 , Y02B60/1228 , Y02B60/142 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.
摘要翻译：接收来自应用的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集和具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。访问来自第一物理地址的与虚拟地址关联的数据和与来自第二物理地址的虚拟地址关联的数据。与对称和非对称存储器组件相关联的数据由应用程序访问，而不向应用程序提供关于在对称存储器组件或非对称存储器组件内访问数据的指示。

5. 发明申请

WO2008055269A3 ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY 审中-公开
标题翻译：混合主存的非对称存储器迁移
公开(公告)号：WO2008055269A3
公开(公告)日：2008-06-26
申请号：PCT/US2007083666
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS INC , KARAMCHETI VIJAY , OKIN KENNETH A , GANAPATHY KUMAR , SINGHAI ASHISH , PAREKH RAJESH
发明人： KARAMCHETI VIJAY , OKIN KENNETH A , GANAPATHY KUMAR , SINGHAI ASHISH , PAREKH RAJESH
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02B60/1225 , Y02B60/1228 , Y02B60/142 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
摘要翻译：主存储器通过接收来自应用程序的命令来读取与映射到主存储器的虚拟地址相关联的数据来进行管理。存储器控制器确定虚拟地址被映射到主存储器的对称存储器组件之一，并且访问指示与虚拟地址相关联的数据如何被访问的存储器使用特性。存储器控制器确定与虚拟地址具有适合于主存储器的非对称存储器组件的访问特性并且将与虚拟地址相关联的数据加载到主存储器的非对称存储器组件。在加载和使用存储器管理单元之后，从应用接收命令以读取与虚拟地址相关联的数据，并且从非对称存储器组件检索与虚拟地址相关联的数据。

6. 发明申请

WO2009102821A2 METHODS AND APPARATUS FOR TWO-DIMENSIONAL MAIN MEMORY 审中-公开
标题翻译：用于二维主存储器的方法和设备
公开(公告)号：WO2009102821A2
公开(公告)日：2009-08-20
申请号：PCT/US2009/033843
申请日：2009-02-11
申请人： VIRIDENT SYSTEMS, INC.
发明人： KARAMCHETI, Vijay , GANAPATHY, Kumar
IPC分类号： G06F12/00 , G11C5/14 , G06F9/34 , G11C7/00
CPC分类号： G11C16/0408 , G06F7/78 , G06F12/0207 , G06F12/0246 , G06F12/0607 , G06F17/30477 , G06F2212/7201 , G06F2212/7208 , G11C16/06 , Y02D10/13
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从属存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收的地址而选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个存储器集成电路，以从存储器集成电路中的选定存储器位置读取数据或向其写入数据。 / p>

7. 发明申请

WO2008051940A3 METHODS AND APPARATUS OF DUAL INLINE MEMORY MODULES FOR FLASH MEMORY 审中-公开
标题翻译：用于闪存存储器的双内存模块的方法和装置
公开(公告)号：WO2008051940A3
公开(公告)日：2008-08-14
申请号：PCT/US2007082162
申请日：2007-10-22
申请人： VIRIDENT SYSTEMS INC , KANAPATHIPPILLAI RUBAN , OKIN KENNETH
发明人： KANAPATHIPPILLAI RUBAN , OKIN KENNETH
IPC分类号： G06F3/00
CPC分类号： G11C16/30 , G11C5/04 , G11C5/14 , G11C16/08 , H01R12/725 , H05K1/0286 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49169
摘要： In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
摘要翻译：在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装数量，并降低闪存DIMM的高度。印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。

8. 发明申请

WO2008039886A3 MAIN MEMORY IN A SYSTEM WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO NON-VOLATILE MEMORY, AND RELATED TECHNOLOGIES 审中-公开
标题翻译：具有配置为控制对非易失性存储器访问的存储器控制器的系统中的主存储器以及相关技术
公开(公告)号：WO2008039886A3
公开(公告)日：2008-08-14
申请号：PCT/US2007079622
申请日：2007-09-27
申请人： VIRIDENT SYSTEMS INC , KARAMCHETI VIJAY , GANAPATHY KUMAR , OKIN KENNETH , PAREKH RAJESH
发明人： KARAMCHETI VIJAY , GANAPATHY KUMAR , OKIN KENNETH , PAREKH RAJESH
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0638 , G06F13/12 , G06F13/1657 , G06F13/1694 , G06F2212/25 , G06F2212/7203 , G11C7/1006 , G11C7/1072 , Y02B60/1228 , Y02D10/14
摘要： An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
摘要翻译：一种装置包括具有多个印刷电路板迹线的印刷电路板，安装在印刷电路板上的存储器控制器，所述存储器控制器耦合到所述多个印刷电路板迹线中的一个或多个印刷电路板迹线，多个非易失性类型的存储器集成电路耦合到所述印刷电路板，以及耦合在所述存储器控制器和所述多个非易失性类型的存储器集成电路之间的多个支持集成电路。

9. 发明申请

WO2008039885A3 SYSTEMS, METHODS, AND APPARATUS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES, AND RELATED TECHNOLOGIES 审中-公开
标题翻译：用于具有非易失性存储器模块的主存储器的系统，方法和装置以及相关技术
公开(公告)号：WO2008039885A3
公开(公告)日：2008-08-14
申请号：PCT/US2007079619
申请日：2007-09-27
申请人： VIRIDENT SYSTEMS INC , KARAMCHETI VIJAY , GANAPATHY KUMAR , OKIN KENNETH , PAREKH RAJESH
发明人： KARAMCHETI VIJAY , GANAPATHY KUMAR , OKIN KENNETH , PAREKH RAJESH
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , Y02D10/14
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non- volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译：公开了一种计算系统，其包括通常为处理器保留的处理器插槽中的存储器控制器。多个非易失性存储器模块可以插入通常为DRAM存储器模块预留的存储器插槽中。可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。存储器控制器控制对非易失性存储器模块的读取和写入访问。存储器插槽通过印刷电路板走线与处理器插座连接。访问非易失性存储器模块的数据通信协议通过印刷电路板迹线并通过通常用于访问DRAM型存储器模块的插座传送。

10. 发明申请

WO2008055270A3 WRITING TO ASYMMETRIC MEMORY 审中-公开
标题翻译：写入不对称记忆
公开(公告)号：WO2008055270A3
公开(公告)日：2008-07-10
申请号：PCT/US2007083668
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS INC , KARAMCHETI VIJAY , OKIN KENNETH A , GANAPATHY KUMAR , SINGHAI ASHISH , PAREKH RAJESH
发明人： KARAMCHETI VIJAY , OKIN KENNETH A , GANAPATHY KUMAR , SINGHAI ASHISH , PAREKH RAJESH
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02B60/1225 , Y02B60/1228 , Y02B60/142 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.
摘要翻译：存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性，写这个地址。非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。

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