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61. 发明申请

WO02086903A3 SEMICONDUCTOR MEMORY ELEMENT 审中-公开
标题翻译：半导体存储元件
公开(公告)号：WO02086903A3
公开(公告)日：2003-10-09
申请号：PCT/DE0201504
申请日：2002-04-24
申请人： INFINEON TECHNOLOGIES AG , OBERGRUSSBERGER FRANZ-XAVER , BAENISCH ANDREAS , ZIMMERMANN ELLEN
发明人： OBERGRUSSBERGER FRANZ-XAVER , BAENISCH ANDREAS , ZIMMERMANN ELLEN
IPC分类号： G11C7/16 , G11C5/06 , G11C8/10 , G11C27/00
CPC分类号： G11C7/16
摘要： According to the invention, a plurality of digital-analogue converters (60, 61) and analogue-digital converters are positioned in the data lines (20, 21) between the connection contacts (3) and the memory cells (1), in such a way that the reading, writing and control of the memory takes place by analogue data transfers instead of the previous digital signatures. It is therefore possible to read, by means of a single connection contact, the same quantity of data, which would usually necessitate several connection contact surfaces (pads). Respective contact surfaces for the analogue line address and the analogue column address are sufficient for addressing the memory cells, said addresses being converted into digital addresses using analogue-digital converters.
摘要翻译：多个数字到模拟的连接触点（3）和所述存储单元之间的转换器（60，61）和模拟 - 数字转换器在所述数据线（20，21）（1）存在时，使得读，写和驱动存储器可以由模拟数据传送，而不是前面的数字信号来完成。需要为常多个端子的接触面（垫）的数据相同量的，因此可以仅由一个端子接触被读出。分别满足接触表面用于模拟行地址和列地址的模拟，其与模拟 - 数字转换器，用于寻址所述存储器单元反应成数字地址。

62. 发明申请

WO02027729A2 WRITABLE TRACKING CELLS 审中-公开
标题翻译：可编程轨道单元
公开(公告)号：WO02027729A2
公开(公告)日：2002-04-04
申请号：PCT/US2001/030123
申请日：2001-09-25
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C27/00 , G11C29/04
CPC分类号： G11C16/28 , G11C7/06 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C27/005 , G11C2211/5621 , G11C2211/5634
摘要： The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.
摘要翻译：本发明涉及使用可写单元的许多技术。为存储器的每个写入块提供多个跟踪单元。每当相关写入块的用户单元被写入时，这些单元被重新编程，优选同时使用相同的固定全局参考电平来定义用户单元的跟踪和编程阈值。在用户单元的每次读取时读取跟踪单元的阈值电压，该阈值用于确定用户单元的注册逻辑电平。在一组实施例中，一个或多个跟踪单元的群体与多状态存储器的不同逻辑级别相关联。这些跟踪细胞群体可以仅提供给逻辑层次的子集。基于该子集为所有逻辑电平获得阈值电压转换的读取点。在一个实施例中，每个由多个检控单元组成的两个群体与多重二进制单元的两个逻辑层次相关联。在类似的实施例中，直接通过跟踪细胞群体的类似阈值来读取用户细胞而不将其翻译成数值。一组变体涉及使用跟踪单元的不同电压和/或时间基准来降低跟踪单元的最终写入阈值的不确定性程度。

63. 发明申请

WO9908284A3 NOVEL MULTI-STATE MEMORY 审中-公开
标题翻译：新的多状态存储器
公开(公告)号：WO9908284A3
公开(公告)日：2001-06-07
申请号：PCT/US9815657
申请日：1998-07-29
申请人： SANDISK CORP
发明人： GUTERMAN DANIEL C , FONG YUPIN KAWING
IPC分类号： G11C16/02 , G11C11/56 , G11C27/00 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
摘要翻译：通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和检测实际的最终数字数据。

64. 发明申请

WO99017296A1 ANALOG MEMORY AND IMAGE PROCESSING SYSTEM 审中-公开
标题翻译：模拟记忆和图像处理系统
公开(公告)号：WO99017296A1
公开(公告)日：1999-04-08
申请号：PCT/JP1998/004309
申请日：1998-09-25
IPC分类号： G11C27/02 , G11C27/04 , G11C27/00 , H04N9/28
CPC分类号： G11C27/04 , G11C27/024
摘要： The fixed pattern noise of an analog memory is reduced. The transmission paths of an address selection signal (SL) between an address generating unit (10) and memory devices (21) are so constructed so that the electrical characteristics when the address selection signal (SL) drives the memory devices (21) are nearly uniform to an extent that fixed pattern noise is not included in the output signal of the analog memory. A buffer unit (50) which stores the address selection signal temporarily and outputs it is provided between the address generating unit (10) and the memory devices (21) and the output characteristics of the buffer unit (50) are uniform for the memory devices (21). Further, the wiring between the buffer unit (50) and the memory devices (21) are so constructed that the electrical characteristics of the wiring are nearly uniform. With this construction, the charge feed-through noise of the memory devices (21) can be nearly uniform, and the fixed pattern noise can be suppressed.
摘要翻译：模拟存储器的固定模式噪声降低。地址生成单元（10）和存储器件（21）之间的地址选择信号（SL）的传输路径被构造成使得当地址选择信号（SL）驱动存储器件（21）时的电特性几乎在模拟存储器的输出信号中不包括固定模式噪声的程度。在地址产生单元（10）和存储装置（21）之间提供临时存储地址选择信号并输出地址选择信号的缓冲单元（50），并且缓冲单元（50）的输出特性对于存储器件是均匀的（21）。此外，缓冲单元（50）和存储器件（21）之间的布线被构造成使得布线的电气特性几乎均匀。利用这种结构，存储器件（21）的电荷馈通噪声可以几乎均匀，并且可以抑制固定图案噪声。

65. 发明申请

WO1996026523A1 AN ITERATIVE METHOD OF RECORDING ANALOG SIGNALS 审中-公开
标题翻译：记录模拟信号的迭代方法
公开(公告)号：WO1996026523A1
公开(公告)日：1996-08-29
申请号：PCT/US1995002258
申请日：1995-02-23
申请人： INFORMATION STORAGE DEVICES, INC.
发明人： INFORMATION STORAGE DEVICES, INC. , SOWARDS, David , BLYTH, Trevor , KHAN, Sakhavat , ENGH, Lawrence
IPC分类号： G11C27/00
CPC分类号： G11C29/44 , G11C27/005
摘要： Method and apparatus for adjustment and control of an iterative method of recording analog signals with on-chip trimming techniques for later playback. The invention allows setting of various parameters for the multi iterative programming technique after chip fabrication so as to allow tighter control and thus higher resolution analog signal sample storage in a given or minimum amount of time. Such parameters include, but are not limited to: the step down voltage [VSD] from the coarse programming cycle to the fine programming cycle, the incremental voltage increase between each fine pulse, the pulse width of each fine pulse, the number of fine pulses [Nf], the incremental voltage increase between each coarse pulse [VC], the pulse width of each coarse pulse, the number of coarse pulses [NC], and the offset [VOS], which stops further coarse pulses and holds the last coarse level as a reference for the following fine cycle.
摘要翻译：用于调整和控制利用片上修剪技术记录模拟信号的迭代方法以用于稍后播放的方法和装置。本发明允许在芯片制造之后设置用于多重编程技术的各种参数，以允许在给定或最短时间内更严格的控制和因此更高分辨率的模拟信号样本存储。这些参数包括但不限于：从粗略编程周期到精细编程周期的降压电压[VSD]，每个精细脉冲之间的增量电压增加，每个精细脉冲的脉冲宽度，细微脉冲数 [Nf]，每个粗略脉冲[VC]，每个粗略脉冲的脉冲宽度，粗略脉冲数[NC]和偏移量[VOS]之间的增量电压增加，停止进一步粗略脉冲并保持最后粗略水平作为以下罚款周期的参考。

66. 发明申请

WO1993022770A1 METHOD AND APPARATUS FOR STORAGE OF DIGITAL INFORMATION 审中-公开
标题翻译：存储数字信息的方法和装置
公开(公告)号：WO1993022770A1
公开(公告)日：1993-11-11
申请号：PCT/US1993003631
申请日：1993-04-16
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , BALLANTYNE, Wayne, W. , REVTAI, George, Jr.
IPC分类号： G11C27/00
CPC分类号： G11C27/005 , G11C7/16 , G11C11/5621 , G11C11/5628 , G11C11/5642
摘要： A method and apparatus for storage of digital information includes an EEPROM (102), a D/A converter (106) and an A/D converter (108). Low-pass filters (104 and 110) are included in order to minimize noise during the conversion process. By converting the digital information to be stored into EEPROM (102) into analog voltages representative of the multi-bit digital information and then reconverting the information when required, an increase in storage capability is realized. This increase in storage capability provides for less expensive storage as compared to use of conventional digital EEPROMs.
摘要翻译：用于存储数字信息的方法和装置包括EEPROM（102），D / A转换器（106）和A / D转换器（108）。包括低通滤波器（104和110），以便在转换过程中最小化噪声。通过将要存储到EEPROM（102）中的数字信息转换为表示多位数字信息的模拟电压，然后在需要时重新转换信息，实现存储能力的提高。与使用常规数字EEPROM相比，存储能力的这种增加提供了较便宜的存储。

67. 发明申请

WO1993011541A1 PROGRAMMABLE NON-VOLATILE ANALOG VOLTAGE SOURCE DEVICES AND METHODS 审中-公开
标题翻译：可编程非易失性模拟电压源器件及方法
公开(公告)号：WO1993011541A1
公开(公告)日：1993-06-10
申请号：PCT/US1992008717
申请日：1992-10-13
申请人： INFORMATION STORAGE DEVICES, INC.
发明人： INFORMATION STORAGE DEVICES, INC. , KHAN, Sakhawat
IPC分类号： G11C27/00
CPC分类号： G11C27/024 , G11C27/005
摘要： Programmable non-volatile analog voltage source devices (20) and methods wherein analog voltages may be sampled and stored in a non-volatile manner for output, typically through parallel output buffers (26). In one form and in a single integrated circuit, an input (VIN) provided to the circuit may be stored at any analog storage location as determined by an address (CS0-CS2) also provided to the circuit, the storage location determining at which of the outputs of the circuit the stored value will appear. While the storage (22), achieved by way of storage of differential voltages in floating gate MOSFET devices, is non-volatile, the same is also electrically alterable as desired. Various alternate embodiments and methods including the ability to address multiple pages of analog storage locations for storage of analog signals and selective parallel output of each page of the storage, output enable capabilities, parallel inputs and digital inputs are disclosed.
摘要翻译：可编程非易失性模拟电压源装置（20）和其中模拟电压可以以非易失性方式进行采样和存储，以通常通过并行输出缓冲器（26）输出的方法。在一种形式和单个集成电路中，提供给电路的输入（VIN）可以存储在由也提供给电路的地址（CS0-CS2）确定的任何模拟存储位置，存储位置确定电路的输出将出现存储值。虽然通过在浮动栅极MOSFET器件中存储差分电压实现的存储器（22）是非易失性的，但是根据需要也可以电可改变。公开了各种替代实施例和方法，包括能够寻址用于存储模拟信号的模拟存储位置的多页和存储，输出使能能力，并行输入和数字输入的每一页的选择性并行输出的能力。

68. 发明申请

WO1993008575A1 RESISTIVE MEMORY ELEMENT 审中-公开
标题翻译：电阻记忆元素
公开(公告)号：WO1993008575A1
公开(公告)日：1993-04-29
申请号：PCT/GB1992001929
申请日：1992-10-20
申请人： LECOMBER, Joy +hf , BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY , ROSE, Mervyn, John , HAJTO, Janos , OWEN, Alan, Ernest , OSBORNE, Ian, Stewart , SNELL, Anthony, James
发明人： LECOMBER, Joy +hf , BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY , LECOMBER, Peter, George +di
IPC分类号： G11C27/00
CPC分类号： G06N3/0635 , G11C27/00
摘要： The resistance of a resistive memory element, e.g. a synaptic element is programmed, e.g. adjusted to a target value, by pulses of a constant height and variable width. One polarity gives an increase in resistance; the other polarity gives a decrease. A short pulse applied after a longer pulse appears to have no effect. After each polarity change short pulses can again be used to make small adjustments. In a preferred embodiment longer and longer pulses are used until the resistance overshoots the target value. After overshooting the polarity is reversed and a second series of pulses is used to obtain a closer approach to the target. The resistive element comprises a resistive layer located between two electrodes, e.g. a matrix of amorphous silicon doped with boron containing V. One electrode is Cr and the other is V.
摘要翻译：电阻式存储元件的电阻，例如突触元件被编程，例如通过恒定高度和可变宽度的脉冲调节到目标值。一个极性使电阻增加; 另一极性降低。较长脉冲后施加的短脉冲似乎没有效果。每个极性变化后，可以再次使用短脉冲进行微调。在优选实施例中，使用更长和更长的脉冲，直到电阻超过目标值。在超调之后，极性反转，并且使用第二系列脉冲来获得对目标的更近的接近。电阻元件包括位于两个电极之间的电阻层，例如。掺杂有硼的非晶硅的矩阵。一个电极是Cr，另一个是V.

69. 发明申请

WO1992005561A1 WRITABLE DISTRIBUTED NON-VOLATILE ANALOG REFERENCE SYSTEM AND METHOD FOR ANALOG SIGNAL RECORDING AND PLAYBACK 审中-公开
标题翻译：可写分配的非易失性模拟参考系统和模拟信号记录和播放的方法
公开(公告)号：WO1992005561A1
公开(公告)日：1992-04-02
申请号：PCT/US1991006891
申请日：1991-09-23
申请人： INFORMATION STORAGE DEVICES, INC.
发明人： INFORMATION STORAGE DEVICES, INC. , SIMKO, Richard
IPC分类号： G11C27/00
CPC分类号： G11C7/16 , G11C27/005 , G11C27/024
摘要： A writable distributed non-volatile analog reference system and method for analog signal recording and playback having application in integrated circuits which sample and directly store analog information (ANAIN). The invention is useful to facilitate the sensing of analog levels stored in nonvolatile memory cells (10) where the analog levels are played back such as to reproduce voice or music or tone information. In accordance with the method, one or more reference storage columns (11L, 11R, 12L, 12R) are included in the array (10) at each side of the storage cell array (10) and are used to store a referene signal at the same time that the adjacent storage cell stores a signal sample. On playback, the stored reference signals for the row of the array are read back and weighted relative to each other in accordance with the relative row position of the signal being taken as the difference between the signal sample read back (VARAY) and the reference signals read back (VREF) (as weighted relative to each other as per the position in the row of the signal cell). The differencing places many error sources in the common mode, thereby substantially eliminating the same from the output signal. A specific memory array organization and the operation thereof is disclosed.

70. 发明申请

WO2023091722A1 ROBUST OVER THE AIR REPROGRAMMING 审中-公开
公开(公告)号：WO2023091722A1
公开(公告)日：2023-05-25
申请号：PCT/US2022/050500
申请日：2022-11-18
申请人： TOYOTA MOTOR NORTH AMERICA, INC.
发明人： CAIN, Jr., Edward Allen , PATNE, Satyajit P. , BARKER, Russell K. , WILSON, Ryan N. , THANICKEL, Ismail
IPC分类号： B60R16/023 , G06F3/06 , G06F16/23 , G11C27/00
摘要： An example operation includes one or more of downloading an update of a non-volatile electrically erasable memory storage of a vehicle, determining whether the memory storage is arranged in one of a block of bytes of memory and an individual byte of memory, selecting a programming protocol based on the memory storage arrangement and writing the memory storage based on the selected programming protocol.

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