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61. 发明申请

WO01054175A1 LOW THREADING DISLOCATION DENSITY RELAXED MISMATCHED EPILAYERS WITHOUT HIGH TEMPERATURE GROWTH 审中-公开
标题翻译：低螺纹偏差密度松动的不配高温无高温生长
公开(公告)号：WO01054175A1
公开(公告)日：2001-07-26
申请号：PCT/US2001/001413
申请日：2001-01-16
IPC分类号： H01L21/205 , C30B25/02 , H01L21/20
CPC分类号： C30B25/02 , C30B29/40 , C30B29/42 , C30B29/52 , H01L21/02381 , H01L21/02392 , H01L21/02395 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/0262
摘要： A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100 DEG C above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100 DEG C above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100 DEG C above the deposition temperature of the second semiconductor layer.
摘要翻译：一种半导体结构及其处理方法，包括：衬底，沉积在衬底上的晶格失配的第一层，并在高于淀积温度的大于100℃的温度下退火;以及沉积在第一层上的第二层，具有较大的晶格与第一半导体层不匹配。在另一个实施方案中，提供半导体衬底上的半导体梯度组合物层结构及其加工方法，其包括半导体衬底，第一半导体层，其具有沉积在衬底上并在较大温度下退火的一系列晶格失配的半导体层比沉积温度高100℃的第二半导体层，与第一半导体层相比，沉积在第一半导体层上与衬底相比具有更大的晶格失配的第二半导体层，并且在比第二半导体层的沉积温度高于100℃的温度下退火半导体层。

62. 发明申请

WO99028958A1 RELAXED InxGA(1-x)As GRADED BUFFERS 审中-公开
标题翻译：放松的InxGA（1-x）作为GRADED BUFFERS
公开(公告)号：WO99028958A1
公开(公告)日：1999-06-10
申请号：PCT/US1998/024921
申请日：1998-11-25
IPC分类号： H01L21/205 , H01L21/20 , H01L21/338 , H01L29/812 , H01S5/323
CPC分类号： H01L21/02543 , H01L21/02395 , H01L21/02463 , H01L21/0251 , H01L21/02546 , Y10S977/712
摘要： InxGa1-xAs structures with compositionally graded buffers (104) grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs (102); and epitaxially growing a relaxed graded layer of InxGa1-xAs (104) at a temperature ranging upwards from about 600 DEG C.
摘要翻译： In x Ga 1-x As结构，其具有在GaAs衬底上用有机金属气相外延（OMPVE）生长的组成梯度缓冲液（104）。一种半导体结构和处理这种结构的方法，包括提供GaAs（102）的衬底; 并在约600℃的温度范围内外延生长In x Ga 1-x As（104）的缓和分级层。

63. 发明申请

WO99021216A1 METHOD FOR EPITACTICAL PRODUCTION OF SEMI-INSULATING III-V COMPOUND SEMICONDUCTORS 审中-公开
标题翻译：用于生产外延SEMI保温III-V族化合物半导体
公开(公告)号：WO99021216A1
公开(公告)日：1999-04-29
申请号：PCT/DE1998/003097
申请日：1998-10-16
IPC分类号： C30B25/02 , H01L21/205 , H01L29/207 , C23C16/30
CPC分类号： C30B25/02 , C30B29/40 , H01L21/02543 , H01L21/02546 , H01L21/02581 , H01L21/0262 , H01L29/207 , H01S5/2226
摘要： The invention relates to insulating III-V compound semiconductors such as, for example, InP and In>x 1-x
摘要翻译：半绝缘III-V族化合物半导体，例如的InP和In> X <镓> 1-x <如当前由与铁，钛，铜或Cl掺杂来制造。然而，经常发生不良现象，例如作为掺杂剂的高扩散性，有p型掺杂剂，结晶质量差和/或用于注入电子和空穴的补偿差交换。在新的方法中，半导体掺杂有钌，在半导体的带隙产生从而深能级，导致减少的载流子浓度的本征浓度的附近。生长半绝缘的Ru掺杂的III-V族半导体例如 InP基涂料，在膦中使用Phosphorprecursorn的少于三个氢原子，有利于。通过Rutheniumdotierung一个载流子补偿可以同时为电子和空穴注入在制成。该方法使得能够沉积半绝缘层，掺杂剂同时具有非常低的扩散系数和不参与与p型掺杂剂交换反应。该方法使得能够使用半绝缘性的半导体层作为绝缘体和/或作为在器件的有源器件层。

64. 发明申请

WO1997017723A1 GaAs SUBSTRATE WITH COMPOSITIONALLY GRADED AlGaAsSb BUFFER FOR FABRICATION OF HIGH-INDIUM FETS 审中-公开
标题翻译：具有组成AlGaAsSb缓冲层的GaAs衬底，用于制造高浓度FET
公开(公告)号：WO1997017723A1
公开(公告)日：1997-05-15
申请号：PCT/US1996017956
申请日：1996-11-08
申请人： LOCKHEED MARTIN CORPORATION
发明人： LOCKHEED MARTIN CORPORATION , GILL, David, M. , UPPAL, Parvez, Nasir
IPC分类号： H01L21/203
CPC分类号： H01L29/1075 , H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/0251 , H01L21/02543 , H01L21/02546
摘要： Semiconductor devices made in high-indium-content semiconductor material (16) have advantageous properties, but similar substrate materials are hard to handle. A buffer layer (18) makes a lattice-constant transition between a GaAs substrate and a high-indium epitaxially deposited semiconductor such as those lattice-matched to InP. The buffer layer (18) is an epitaxial layer including atoms of two Group III elements, and atoms of two Group V elements, with the ratio of the atoms of at least one group varied along the depth of the buffer layer, in a manner which makes a transition of the lattice constant between that of the substrate and the high-indium semiconductor material. The Group III elements are gallium and aluminum, and the Group V elements are arsenic and antimony.
摘要翻译：在高铟含量半导体材料（16）中制造的半导体器件具有有利的性质，但类似的衬底材料难以处理。缓冲层（18）在GaAs衬底和高铟铟外延沉积半导体之间形成晶格常数转变，例如与InP晶格匹配的那些。缓冲层（18）是包含两个III族元素的原子和两个V族元素的原子的外延层，其中至少一个原子的比例沿缓冲层的深度变化，其方式为使晶格常数与基板和高铟半导体材料的晶格常数的转变。 III族元素是镓和铝，V族元素是砷和锑。

65. 发明申请

WO1996027207A1 III-V SEMICONDUCTOR COMPONENT AND METHOD FOR MAKING SAME 审中-公开
标题翻译： III-V半导体元件及其制造方法
公开(公告)号：WO1996027207A1
公开(公告)日：1996-09-06
申请号：PCT/FR1996000304
申请日：1996-02-27
申请人： PICOGIGA , NUYEN, Linh, T.
发明人： PICOGIGA
IPC分类号： H01L21/20
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02395 , H01L21/02543 , H01L21/02546 , H01L2221/68363
摘要： A method wherein (a) an epitaxy substrate (1) made of a first III-V semiconductor material is produced; (b) an intermediate film (2) made of a second III-V semiconductor material having a different chemical composition from the first material is formed by epitaxy on the epitaxy substrate (1); (c) a first active thin film (3) made of a III-V semiconductor material having a different chemical composition from the second material is formed by epitaxy on the intermediate film (2); (d) at least one further active thin film (4) made of a III-V semiconductor material is formed by epitaxy on said first active thin film (3); (e) a planar supporting substrate (5) is produced; (f) the resulting structure is turned over and placed against the planar supporting substrate (5); and (g) the first and second materials are selectively etched to remove the epitaxy substrate (1) and the intermediate film (2), whereby the surface of the supporting substrate (5) is adhered to the other active thin film (3, 4) or to the last of the other epitaxial active thin films by means of a simple van der Waals interaction between the two mutually facing surfaces.
摘要翻译：一种方法，其中（a）由第一III-V族半导体材料制成的外延衬底（1）; （b）由外延基板（1）上的外延形成由具有与第一材料不同的化学成分的由第二III-V族半导体材料制成的中间膜（2）（c）在中间膜（2）上通过外延形成由具有与第二材料不同的化学组成的III-V族半导体材料制成的第一有源薄膜（3）。（d）在所述第一有源薄膜（3）上通过外延形成至少一个由III-V半导体材料制成的其它有源薄膜（4）。（e）制造平面支撑衬底（5）; （f）将所得结构翻转并放置在平面支撑基底（5）上; 并且（g）选择性地蚀刻第一和第二材料以去除外延衬底（1）和中间膜（2），由此支撑衬底（5）的表面粘附到另一个有源薄膜（3,4））或通过在两个相互面对的表面之间的简单的范德华相互作用到最后的其它外延活性薄膜。

66. 发明申请

WO1993009569A1 METHOD FOR PRODUCING OPTO-ELECTRONIC COMPONENTS BY SELECTIVE EPITAXY IN A GROOVE 审中-公开
标题翻译：通过选择性外延在栅格中生产光电子元件的方法
公开(公告)号：WO1993009569A1
公开(公告)日：1993-05-13
申请号：PCT/FR1992001029
申请日：1992-11-05
申请人： FRANCE TELECOM , ALLOVON, Michel , ROSE, Benoît
发明人： FRANCE TELECOM
IPC分类号： H01L33/00
CPC分类号： H01L33/0062 , H01L21/02392 , H01L21/02461 , H01L21/02463 , H01L21/02507 , H01L21/02543 , H01L21/02546 , H01S5/026 , H01S5/106 , H01S5/227 , H01S5/2272 , H01S5/32391 , H01S5/3428
摘要： A method wherein the active strip (112, 114, 116, 118) of a component is produced by selective epitaxy in a groove which has been etched in a semi-insulating material by means of a mask consisting of two strips (B1, B2). The method may be used to produce integrated laser and modulator components.

67. 发明申请

WO1989004551A1 III-V SEMICONDUCTOR GROWTH INITIATION ON SILICON 审中-公开
标题翻译： III-V半导体生长在硅上的发展
公开(公告)号：WO1989004551A1
公开(公告)日：1989-05-18
申请号：PCT/US1988004013
申请日：1988-11-09
申请人： KOPIN CORPORATION
发明人： KOPIN CORPORATION , LEE, Jhang, Woo , McCULLOUGH, Richard, E. , SALERNO, Jack, P.
IPC分类号： H01L21/205
CPC分类号： H01L21/02546 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02513 , H01L21/02543 , H01L21/0262 , Y10S148/065 , Y10S148/072 , Y10S148/11 , Y10S148/149 , Y10S148/169 , Y10S438/933
摘要： A GaAs containing nucleation layer is deposited upon Si, Ge/Si, or other single crystal substrate from triethyl gallium (TEG). Deposition from TEG allows a lower deposition temperature which provides a low level of substrate contamination and improved surface morphology.

68. 发明申请

WO8904548A2 ION IMPLANTATION AND ANNEALING OF COMPOUND SEMICONDUCTOR LAYERS 审中-公开
标题翻译：复合半导体层的离子植入和退火
公开(公告)号：WO8904548A2
公开(公告)日：1989-05-18
申请号：PCT/US8804010
申请日：1988-11-09
申请人： KOPIN CORP
发明人： FAN JOHN C C , LEE JHANG WOO , NARAYAN JAGDISH
IPC分类号： H01L21/20 , H01L33/00
CPC分类号： H01L33/0095 , H01L21/02381 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/02694 , H01L33/0066 , Y10S148/065 , Y10S148/072 , Y10S148/084 , Y10S148/149 , Y10S438/933
摘要： A method for reducing the defect and dislocation density in III-V material layers deposited on dissimilar substrates is disclosed. The method involves ion implantation of dopant materials to create amorphous regions within the layers followed by an annealing step during which the amorphous regions are recrystallized to form substantially monocrystalline regions. The wafers produced by the process are particularly well suited for optoelectronic devices.

69. 发明申请

WO1987000694A1 METHOD FOR PRODUCING A HETEROSTRUCTURE DEVICE 审中-公开
标题翻译：用于生产异构体装置的方法
公开(公告)号：WO1987000694A1
公开(公告)日：1987-01-29
申请号：PCT/GB1986000423
申请日：1986-07-18
申请人： PLESSEY OVERSEAS LIMITED , SCOTT, Michael, Darak , MOORE, Alan, Howard
发明人： PLESSEY OVERSEAS LIMITED
IPC分类号： H01L33/00
CPC分类号： B82Y20/00 , H01L21/02392 , H01L21/0243 , H01L21/02433 , H01L21/02461 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L21/30617 , H01L33/0062 , H01S5/20 , H01S5/2201 , H01S5/227 , H01S5/2275 , H01S5/32391 , H01S5/343 , Y10S148/029 , Y10S148/065 , Y10S148/072 , Y10S148/119
摘要： A method of producing a heterostructure device comprises defining in a substrate (5) of group III-V semiconductor material a structure, such as a mesa (9), having first and second faces oriented substantially parallel to the [100] and A crystallographic planes. The mesa (9) is exposed to group III-V chemical reagents thereby to deposit group III-V materials on the first and/or second faces in dependence upon the group V constituent in the chemical reagents.
摘要翻译：一种制造异质结构器件的方法包括在III-V族半导体材料的衬底（5）中限定具有基本上平行于[100]和[111]的第一和第二面的结构，例如台面（9）一个结晶平面。将台面（9）暴露于III-V族化学试剂，从而根据化学试剂中的V族成分将III-V族材料沉积在第一和/或第二面上。

70. 发明申请

WO1986004734A1 GROWTH OF LATTICE-GRADED EPILAYERS 审中-公开
标题翻译：增长幅度的增长
公开(公告)号：WO1986004734A1
公开(公告)日：1986-08-14
申请号：PCT/US1985001117
申请日：1985-06-20
申请人： COOK, Melvin, S.
IPC分类号： H01L21/20
CPC分类号： C30B25/02 , C30B25/04 , C30B25/18 , C30B29/40 , C30B29/607 , H01L21/02381 , H01L21/02543 , H01L21/02546 , H01L31/036 , Y10S117/902 , Y10S148/067 , Y10S148/072 , Y10S148/097 , Y10S148/16 , Y10S438/936 , Y10S438/938
摘要： A method for growing an epitaxial layer (77) composed of semiconductor material belonging to the cubic crystal system on a substrate (71), where the lattice constant of the epitaxial layer is graded from an initial lattice constant adjacent to the substrate (71) to a final lattice constant on the surface of the epitaxial layer (77). Growth surfaces (79) are formed on the substrate, and the epitaxial layer (77) is grown as its lattice constant changes from the initial lattice constant to the final lattice constant.
摘要翻译：一种用于在衬底（71）上生长由属于立方晶系的半导体材料构成的外延层（77）的方法，其中外延层的晶格常数从邻近衬底（71）的初始晶格常数分级到在外延层（77）的表面上的最终晶格常数。生长表面（79）形成在衬底上，并且外延层（77）随其晶格常数从初始晶格常数变化到最终晶格常数而生长。

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