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61. 发明申请

WO1996010840A1 IMPROVED ISOLATION BETWEEN DIFFUSION LINES IN A MEMORY ARRAY 审中-公开
标题翻译：在存储阵列中扩展线之间的改进隔离
公开(公告)号：WO1996010840A1
公开(公告)日：1996-04-11
申请号：PCT/US1995011563
申请日：1995-09-13
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , ONG, Tong-Chern , TANG, Daniel, N.
IPC分类号： H01L21/8246
CPC分类号： H01L21/7621 , H01L21/76216 , H01L21/76221 , H01L27/105 , H01L27/11521
摘要： A method of forming a memory device with improved isolation between diffusion lines. Parallel, spaced apart thick oxide strips (201) are grown on a substrate. Next, spaced apart, parallel strips (302) having a polysilicon (302a) and nitride (302b) layer, oriented perpendicular to the first strips (201), are formed. The oxide (201) between the second strips is removed, followed by an implantation to form source (402) and drain (401) regions. The nitride layer (302b) on the second strips is removed on those strips between two drain diffusions (401) and an oxidation is performed to form self-aligned thick oxide (602) over the source and drain regions. The strips from which the nitride has been removed are also oxidized, thus providing isolation between adjacent drain lines.
摘要翻译：一种形成具有改善的扩散线隔离的存储器件的方法。在衬底上生长平行的间隔开的厚氧化物条（201）。接下来，形成具有垂直于第一条带（201）定向取向的间隔开的具有多晶硅（302a）和氮化物（302b）层的平行条带（302）。去除第二条带之间的氧化物（201），随后进行注入以形成源极（402）和漏极（401）区域。第二条带上的氮化物层（302b）在两个漏极扩散（401）之间的那些条上被去除，并且在源极和漏极区域上进行氧化以形成自对准的厚氧化物（602）。去除氮化物的条带也被氧化，从而在相邻的排水管线之间提供隔离。

62. 发明申请

WO1996007970A1 METHOD AND APPARATUS FOR PERFORMING DEFERRED TRANSACTIONS 审中-公开
标题翻译：执行延期交易的方法和装置
公开(公告)号：WO1996007970A1
公开(公告)日：1996-03-14
申请号：PCT/US1995011315
申请日：1995-09-08
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , SARANGDHAR, Nitin, V. , LAI, Konrad, K. , SINGH, Gurbir , MACWILLIAMS, Peter, D.
IPC分类号： G06F13/14
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus for performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens (302) between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：一种用于在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌（302），而不使用专用令牌总线。

63. 发明申请

WO1996000976A1 PROCESSOR THAT INDICATES SYSTEM BUS OWNERSHIP IN AN UPGRADABLE MULTIPROCESSOR COMPUTER SYSTEM 审中-公开
标题翻译：在可升级的多处理器计算机系统中显示系统总线所有权的处理器
公开(公告)号：WO1996000976A1
公开(公告)日：1996-01-11
申请号：PCT/US1995007308
申请日：1995-06-08
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , KRICK, Robert, F. , FERNANDO, Roshan, J.
IPC分类号： H01J13/00
CPC分类号： G06F13/24
摘要： A computer system (100) having a processor (10, 12) with a type input pin (22, 24) that indicates whether the processor (10, 12) is coupled as an OEM processor (10) in a single processor or a dual processor computer system. The processor includes an upgrade processor (12) in the dual processor computer system. The processor includes an upgrade/OEM output pin coupled to transfer an upgrade/OEM signal over a system bus (16) if the type input pin (22, 24) indicates the OEM processor (10). The upgrade/OEM signal indicates whether the OEM processor (10) or the upgrade processor (12) is a bus owner of the system bus (16).
摘要翻译：具有处理器（10,12）的计算机系统（100）具有类型输入引脚（22,24），其指示所述处理器（10,12）是否作为OEM处理器（10）耦合在单个处理器或双处理器计算机系统。处理器包括双处理器计算机系统中的升级处理器（12）。如果类型输入引脚（22,24）指示OEM处理器（10），则处理器包括耦合以通过系统总线（16）传送升级/ OEM信号的升级/ OEM输出引脚。升级/ OEM信号指示OEM处理器（10）或升级处理器（12）是否是系统总线（16）的总线所有者。

64. 发明申请

WO1995035540A1 DYNAMIC PROCESSOR PERFORMANCE AND POWER MANAGEMENT IN A COMPUTER SYSTEM 审中-公开
标题翻译：计算机系统中的动态处理器性能和电源管理
公开(公告)号：WO1995035540A1
公开(公告)日：1995-12-28
申请号：PCT/US1995007668
申请日：1995-06-14
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , NORRIS, David
IPC分类号： G06F13/00
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , G06F11/34 , G06F11/3419 , G06F13/4243 , Y02D10/124 , Y02D10/126 , Y02D10/151 , Y02D10/34
摘要： A computer system (10) is disclosed comprising a clock generator circuit (14) having a clock speed register (34) and circuitry for generating a processor clock signal (32) at a frequency determined by the clock speed register (34), wherein the processor (12) executes a performance manager program (44) that writes the clock speed register (34) according to a performance state selected by an application program (50, 52). The application program (50, 52) selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions.
摘要翻译：公开了一种计算机系统（10），包括具有时钟速度寄存器（34）的时钟发生器电路（14）和用于以由时钟速度寄存器（34）确定的频率产生处理器时钟信号（32）的电路，其中，处理器（12）执行根据由应用程序（50,52）选择的性能状态来写入时钟速度寄存器（34）的性能管理器程序（44）。应用程序（50,52）选择性能状态以在处理器密集功能期间最大化性能，并且在交互功能期间最大化功率节省。

65. 发明申请

WO1995032470A1 METHOD AND APPARATUS FOR AUTOMATICALLY SCRUBBING ECC ERRORS IN MEMORY VIA HARDWARE 审中-公开
标题翻译：用于通过硬件自动擦除存储器中的ECC错误的方法和装置
公开(公告)号：WO1995032470A1
公开(公告)日：1995-11-30
申请号：PCT/US1995006548
申请日：1995-05-23
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION
IPC分类号： G06F11/10
CPC分类号： G06F11/106 , G06F11/1056
摘要： The present invention provides a method and apparatus for automatically scrubbing ECC errors in memory upon the detection of a correctable error in data read from memory. This is performed by providing in a memory controller (MC) memory control logic for controlling accesses to memory, an ECC error checking and correcting unit for checking data read from memory for errors and correcting any correctable errors found in the read data, a first data buffer for storing the corrected read data output (72, 64) from the ECC error checking and correcting unit and a writeback path having an input end coupled to an output of the first data buffer and an output end coupled to memory. Upon the detection of a correctable error in data read from a particular memory location, the ECC error checking and correcting unit signals to the memory control logic the existence of a correctable error in the read data. The memory control logic then obtains exclusive control over the first data buffer and the writeback path to control writing of the corrected read data onto the writeback path and subsequently to memory.
摘要翻译：本发明提供一种用于在检测到从存储器读取的数据中的可校正误差时自动擦除存储器中的ECC错误的方法和装置。这通过在用于控制对存储器的访问的存储器控制器（MC）存储器控制逻辑中提供，ECC错误检查和校正单元，用于检查从存储器读取的数据的错误并校正在读取的数据中发现的任何可校正的错误，第一数据用于存储来自ECC错误检查和校正单元的校正的读取数据输出（72,64）的缓冲器和具有耦合到第一数据缓冲器的输出的输入端的写回路径和耦合到存储器的输出端。在检测到从特定存储器位置读取的数据中的可校正错误时，ECC错误检查和校正单元向存储器控制逻辑信号发送读取数据中存在可校正错误。存储器控制逻辑然后获得对第一数据缓冲器和写回路径的排他控制，以控制将校正后的读取数据写入写回路径并随后到存储器。

66. 发明申请

WO1995027974A1 PROCESS, APPARATUS, AND SYSTEM FOR COLOR CONVERSION OF IMAGE SIGNALS 审中-公开
标题翻译：图像信号颜色转换的过程，设备和系统
公开(公告)号：WO1995027974A1
公开(公告)日：1995-10-19
申请号：PCT/US1995004026
申请日：1995-04-07
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , KEITH, Michael , WOOD, Stephen
IPC分类号： G09G05/06
CPC分类号： G09G5/06 , G09G3/2051
摘要： A process, apparatus, and system for generating and using lookup tables to convert image signals from a multi-component format to a single-index CLUT format for an arbitrary CLUT palette. In a preferred embodiment, lookup tables are generated for an arbitrary CLUT palette and used to convert (with Y, U, and V dithering) three-component subsampled YUV9 video signals to 8-bit CLUT signals.
摘要翻译：用于生成和使用查找表以将图像信号从多分量格式转换成用于任意CLUT调色板的单索引CLUT格式的过程，装置和系统。在优选实施例中，为任意CLUT调色板生成查找表，并用于将（Y，U和V抖动）三分量二次采样YUV9视频信号转换为8位CLUT信号。

67. 发明申请

WO1995024678A2 HIGHLY PIPELINED BUS ARCHITECTURE 审中-公开
标题翻译：高度管道总线架构
公开(公告)号：WO1995024678A2
公开(公告)日：1995-09-14
申请号：PCT/US1995002505
申请日：1995-03-01
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , SARANGDHAR, Nitin, V. , SINGH, Gurbir , LAI, Konrad
IPC分类号： G06F00/00
CPC分类号： G06F13/18 , G06F12/0831
摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
摘要翻译：描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

68. 发明申请

WO1995010911A1 METHOD AND SYSTEM FOR MULTICASTING RELATED DATA STREAMS ON A COMPUTER NETWORK 审中-公开
标题翻译：用于在计算机网络上组织相关数据流的方法和系统
公开(公告)号：WO1995010911A1
公开(公告)日：1995-04-20
申请号：PCT/US1994011278
申请日：1994-10-06
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , SIVAKUMAR, Ramamurthy , ACOTT, Troy , DANNEELS, Gunner , KEMBEL, John , SAMPAT, Ketan , SPOONER, Galen
IPC分类号： H04L29/06
CPC分类号： H04L12/1859 , H04L29/06
摘要： A plurality of data streams are provided, where at least one data stream is related to at least one other data stream. The data streams are transmitted on a computer network having a plurality of clients. Each client selectively receives zero, one, or more of the transmitted data streams. In a preferred embodiment, audio, video, and/or text data streams may be logically related together to form channels that are transmitted by a server and selectively received and processed (e.g., played or recorded) by the clients.
摘要翻译：提供多个数据流，其中至少一个数据流与至少一个其他数据流相关。数据流在具有多个客户端的计算机网络上传输。每个客户端选择性地接收零个，一个或多个所发送的数据流。在优选实施例中，音频，视频和/或文本数据流可以在逻辑上相关联以形成由服务器发送并由客户端选择性地接收和处理（例如，播放或记录）的信道。

69. 发明申请

WO1993025970A1 A NEURAL NETWORK WITH MULTIPLEXED SYNAPTIC PROCESSING 审中-公开
标题翻译：具有多路复用处理的神经网络
公开(公告)号：WO1993025970A1
公开(公告)日：1993-12-23
申请号：PCT/US1993004920
申请日：1993-05-25
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , HOLLER, Mark, A. , TAM, Simon, M.
IPC分类号： G06F15/18
CPC分类号： G06N3/063 , G06N3/0635
摘要： In an apparatus for multiplexed operation of multi-cell neural network, the reference vector component values are stored as differential values (Wi,j) in pairs of floating gate transistors (101). A long-tail differential transconductance multiplier (131) is synthesized by selectively using the floating gate transistor pairs (101) as the current source. Appropriate transistor pairs (101) are multiplexed into the network for forming a differential output current (delta I) representative of the product (2j, 2j+1) of the input vector component applied to the differential input (104) and the stored reference vector component (Wi,j) stored in the multiplexed transistor pair (101) that is switched into the multiplier network to function as the differential current source. Pipelining and output multiplexing is also described in other preferred embodiments for increasing the effective output bandwidth of the network.

70. 发明申请

WO1993012484A1 A CACHE MEMORY HIERARCHY THAT REDUCES POWER CONSUMPTION BY REDUCING ACCESSES TO MAIN MEMORY 审中-公开
标题翻译：通过减少访问主存储器来降低功耗的缓存记忆分级
公开(公告)号：WO1993012484A1
公开(公告)日：1993-06-24
申请号：PCT/US1992011138
申请日：1992-12-16
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , MATHEWS, Gregory, S. , ZAGER, Edward, S.
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , Y02D10/13
摘要： A cache memory hierarchy having a first level write through cache memory (14) and a second level write back cache memory (20) is provided to a computer system. The first write through cache memory is optimized to provide a high cache read it for read cycles performed by the CPU. The second level write back cache memory is optimized to complement the first level write through cache memory. As a result, accesses to main memory are reduced with minimal increase in complexity and performance cost, thereby reducing power consumption of the computer system in a desirable manner.
摘要翻译：具有通过高速缓存存储器（14）和第二级回写高速缓存存储器（20）具有第一级写入的高速缓冲存储器层级被提供给计算机系统。首次通过高速缓冲存储器写入被优化，以提供高速缓存读取CPU执行的读取周期。第二级回写高速缓存内存被优化，以补充通过高速缓存的第一级写入。结果，通过最小的复杂性和性能成本的增加来减少对主存储器的访问，从而以期望的方式降低计算机系统的功耗。

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