专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

WO2007140037A3 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING AN INTERLAYER AND STRUCTURE THEREOF 审中-公开
标题翻译：形成具有中间层及其结构的半导体器件的方法
公开(公告)号：WO2007140037A3
公开(公告)日：2008-12-24
申请号：PCT/US2007064482
申请日：2007-03-21
申请人： FREESCALE SEMICONDUCTOR INC , SCHAEFFER JAMES K , HEGDE RAMA I , SAMAVEDAM SRIKANTH B
发明人： SCHAEFFER JAMES K , HEGDE RAMA I , SAMAVEDAM SRIKANTH B
IPC分类号： H01L21/8234
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4966 , H01L29/517
摘要： A stack (30) located over a substrate (10). The stack includes a layer (24) between a dielectric layer (16) and a metal layer (26). The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.
摘要翻译：位于衬底（10）上方的堆叠（30）。叠层包括介电层（16）和金属层（26）之间的层（24）。该层包括卤素和金属。在一个实施方案中，卤素是氟。在一个实施例中，堆叠是用于晶体管的控制电极堆叠。在一个示例中，控制电极堆叠是用于MOSFET的栅极堆叠。在一个实例中，该层包括氟化铝。

52. 发明申请

WO2007056093A2 REPLACEMENT METAL GATE TRANSISTORS WITH REDUCED GATE OXIDE LEAKAGE 审中-公开
标题翻译：更换具有减少栅极氧化物泄漏的金属栅极晶体管
公开(公告)号：WO2007056093A2
公开(公告)日：2007-05-18
申请号：PCT/US2006042870
申请日：2006-11-02
申请人： ADVANCED MICRO DEVICES INC , PAN JAMES , PELLERIN JOHN
发明人： PAN JAMES , PELLERIN JOHN
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/28238 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer (70) between the gate oxide layer (12) and metal gate electrode (60), thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon (70) containing metal carbides decreasing in concentration from the metal gate electrode (60) toward the gate oxide layer (12) across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode (60) and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer (70), thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer (82) having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode (100) and substrate (10).
摘要翻译：通过在栅极氧化物层（12）和金属栅电极（60）之间形成保护层（70）来实现用于替换金属栅极晶体管的具有减小的泄漏的薄的有效栅极氧化物厚度，从而减小应力。实施例包括：形成非金属碳（70）的保护层，该保护层含有金属碳化物，金属碳化物的浓度从金属栅电极（60）朝向栅极氧化物层（12）跨越保护层。方法的实施例包括去除可移除栅极，在栅极氧化物层上沉积无定形碳层，形成金属栅电极（60），然后在高温下加热以使金属从金属栅电极扩散到无定形碳层（ 70），从而形成金属碳化物。实施例还包括具有高介电常数的栅极氧化物层（82）和在与金属栅电极（100）和衬底（10）的界面处集中的硅的金属栅极晶体管。

53. 发明申请

WO2007055853A2 ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION ADJACENT TO A STRESSOR LAYER AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 审中-公开
标题翻译：包括具有与激励区邻近的晶体管结构的电子器件以及形成电子器件的工艺
公开(公告)号：WO2007055853A2
公开(公告)日：2007-05-18
申请号：PCT/US2006039650
申请日：2006-10-10
申请人： FREESCALE SEMICONDUCTOR INC , ADAMS VANCE H , GRUDOWSKI PAUL A , KOLAGUNTA VENKAT R , WINSTEAD BRIAN A
发明人： ADAMS VANCE H , GRUDOWSKI PAUL A , KOLAGUNTA VENKAT R , WINSTEAD BRIAN A
IPC分类号： H01L29/792
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device (10) can include a transistor structure (50) of a first conductivity type, a field isolation region (22), and a layer (130) of a first stress type overlying the field isolation region. For example, the transistor structure (50) may be a p-channel transistor structure (50) and the first stress type may be tensile, or the transistor structure (60) may be an n- channel transistor structure and the first stress type (70) may be compressive. The transistor structure (50) can include a channel region (54) that lies within an active region. An edge of the active region includes the interface between the channel region (54) and the field isolation region (22). From a top view, the layer can include an edge that lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region (54) of the transistor structure (50).
摘要翻译：电子器件（10）可以包括第一导电类型的晶体管结构（50），场隔离区（22）以及覆盖场隔离区的第一应力类型的层（130）。例如，晶体管结构（50）可以是p沟道晶体管结构（50），并且第一应力类型可以是拉伸的，或者晶体管结构（60）可以是n沟道晶体管结构并且第一应力类型 70）可能是压缩的。晶体管结构（50）可以包括位于有源区内的沟道区（54）。有源区的边缘包括沟道区（54）和场隔离区（22）之间的界面。从顶视图看，该层可以包括位于有源区边缘附近的边缘。边缘之间的位置关系会影响晶体管结构（50）的沟道区（54）内的载流子迁移率。

54. 发明申请

WO2007009846A1 CMOS TRANSISTORS WITH DUAL HIGH-K GATE DIELECTRIC AND METHODS OF MANUFACTURE THEREOF 审中-公开
标题翻译：具有双高K栅电介质的CMOS晶体管及其制造方法
公开(公告)号：WO2007009846A1
公开(公告)日：2007-01-25
申请号：PCT/EP2006/063067
申请日：2006-06-09
申请人： INFINEON TECHNOLOGIES AG , LI, Hong-Jyh
发明人： LI, Hong-Jyh
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28097 , H01L21/823462 , H01L21/823857 , H01L28/56 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： CMOS devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. A CMOS device is formed on a workplace having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric V1 for the PMOS and NMOS FETs.
摘要翻译：公开了具有不同栅介电材料的晶体管的CMOS器件及其制造方法。在具有第一区域和第二区域的工作区上形成CMOS器件。在第二区域上沉积第一栅极电介质材料。第一栅极材料沉积在第一栅极电介质材料上。包括与第一栅极电介质材料不同的材料的第二栅极电介质材料沉积在工件的第一区域上。第二栅极材料沉积在第二栅极电介质材料上。然后对第一栅极材料，第一栅极电介质材料，第二栅极材料和第二栅极电介质材料进行构图以形成具有用于PMOS和NMOS FET的对称V1的CMOS器件。

55. 发明申请

WO2006063958A3 METHOD FOR PRODUCING AN ELECTRODE 审中-公开
标题翻译：方法制造电极
公开(公告)号：WO2006063958A3
公开(公告)日：2006-11-02
申请号：PCT/EP2005056552
申请日：2005-12-07
申请人： AIXTRON AG , BAUMANN PETER , LINDNER JOHANNES , SCHUMACHER MARCUS
发明人： BAUMANN PETER , LINDNER JOHANNES , SCHUMACHER MARCUS
IPC分类号： H01L29/49 , H01L21/28 , H01L21/285
CPC分类号： H01L27/10873 , H01L21/28088 , H01L27/1085 , H01L29/4966
摘要： The invention relates to a method for producing an electrode (1), which interacts with an active layer (8) of a semiconductor component or dielectric. The working function (Wf) of the electrode (1) is adapted to the position of the energy bands (Ec, Ev) in the layer (8) while taking into account the layer property, particularly the doping of the layer (8). The process is rendered economical by virtue of the fact that a metal/non-metal combination is selected as the electrode material, and the working function (F) is set by varying at least one non-metallic component.
摘要翻译：本发明涉及一种用于制造电极（1），其与活性层相互作用（8）的半导体器件或电介质，（1）（考虑到层属性的电极的功函数（WF），特别是层8的掺杂）（在能带的Ec，EV）的位置适合于在层（8）。该过程是在一个金属/非金属化合物经济被选择作为电极材料，并通过改变至少一个非金属成分的功函数（F）被调整。

56. 发明申请

WO2006055226A2 NITROGEN-CONTAINING FIELD EFFECT TRANSISTOR GATE STACK CONTAINING A THRESHOLD VOLTAGE CONTROL LAYER FORMED VIA DEPOSITION OF A METAL OXIDE 审中-公开
标题翻译：包含金属氧化物沉积形成的阈值电压控制层的含氮场效应晶体管栅格堆叠
公开(公告)号：WO2006055226A2
公开(公告)日：2006-05-26
申请号：PCT/US2005/039288
申请日：2005-11-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BOJARCZUK, Nestor A., Jr. , CABRAL, Cyril, Jr. , CARTIER, Eduard A. , FRANK, Martin M. , GOUSEV, Evgeni P. , GUHA, Supratik , JAMISON, Paul C. , JAMMY, Rajarao , NARAYANAN, Vijay , PARUCHURI, Vamsi K.
发明人： BOJARCZUK, Nestor A., Jr. , CABRAL, Cyril, Jr. , CARTIER, Eduard A. , FRANK, Martin M. , GOUSEV, Evgeni P. , GUHA, Supratik , JAMISON, Paul C. , JAMMY, Rajarao , NARAYANAN, Vijay , PARUCHURI, Vamsi K.
IPC分类号： H01L29/94
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/2822 , H01L21/823828 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518
摘要： A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.
摘要翻译：提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，其条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。本发明还提供一种制造这种结构的方法。

57. 发明申请

WO2006033746A2 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL LAYER 审中-公开
标题翻译：形成具有金属层的半导体器件的方法
公开(公告)号：WO2006033746A2
公开(公告)日：2006-03-30
申请号：PCT/US2005029772
申请日：2005-08-23
申请人： FREESCALE SEMICONDUCTOR INC , STEVENS TAB A , GOOLSBY BRIAN J , NGUYEN BICH-YEN , THEAN VOON-YEW
发明人： STEVENS TAB A , GOOLSBY BRIAN J , NGUYEN BICH-YEN , THEAN VOON-YEW
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/785 , Y10S438/963
摘要： A metal layer (24) is formed over a metal oxide (14), where the metal oxide is formed over a semiconductor substrate (12). A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings (26) at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer (22) is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
摘要翻译：在金属氧化物（14）上形成金属层（24），其中在半导体衬底（12）上形成金属氧化物。确定金属层的预定临界尺寸。执行第一蚀刻以将金属层向下蚀刻到金属氧化物并在金属层的侧壁处形成基脚（26）。用于移除基脚以靶向预定临界尺寸的第二蚀刻，其中第二蚀刻对金属氧化物是选择性的。在一个实施例中，在金属层上形成导电层（22）。可以蚀刻导电层的主体，留下与金属层接触的部分。接下来，可以使用化学选择性地蚀刻与金属层接触的部分。

58. 发明申请

WO2006014401A1 A METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC LAYER AND A METAL GATE ELECTRODE 审中-公开
标题翻译：制备具有高K栅介质层和金属栅极电极的半导体器件的方法
公开(公告)号：WO2006014401A1
公开(公告)日：2006-02-09
申请号：PCT/US2005/023734
申请日：2005-06-30
申请人： INTEL CORPORATION , BRASK, Justin , BARNS, Chris , DOCZY, Mark , SHAH, Uday , KAVALIEROS, Jack , METZ, Matthew , DATTA, Suman , MILLER, Anne , CHAU, Robert
发明人： BRASK, Justin , BARNS, Chris , DOCZY, Mark , SHAH, Uday , KAVALIEROS, Jack , METZ, Matthew , DATTA, Suman , MILLER, Anne , CHAU, Robert
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28185 , H01L21/28194 , H01L21/28229 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成电介质层，在电介质层内形成沟槽，并在沟槽内形成高k栅介质层。在高k栅介质层上形成第一金属层之后，在第一金属层上形成第二金属层。使用抛光步骤从电介质层上方去除第二金属层的至少一部分，并且使用蚀刻步骤从电介质层上方除去附加材料。

59. 发明申请

WO2005048320A2 METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FORM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE 审中-公开
标题翻译：集成具有不同工作功能的金属以形成具有高K栅介电及相关结构的CMOS栅极的方法
公开(公告)号：WO2005048320A2
公开(公告)日：2005-05-26
申请号：PCT/US2004028486
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES INC , XIANG QI , ZHONG HUICAI , GOO JUNG-SUK , HOLBROOK ALLISON KAY , JEON JOONG S , KLUTH GEORGE JONATHAN
发明人： XIANG QI , ZHONG HUICAI , GOO JUNG-SUK , HOLBROOK ALLISON KAY , JEON JOONG S , KLUTH GEORGE JONATHAN
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/00
CPC分类号： H01L21/823857 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for integrating first (206) and second metal layers (208) on a substrate (202) to form a dual metal NMOS gate (226) and PMOS gate (228) comprises depositing (150) a dielectric layer (204) over an NMOS region (210) and a PMOS region (212) of the substrate (202). The method further comprises depositing (150) the first metal layer (206) over dielectric layer (204). The method further comprises depositing (150) the second metal layer (208) over the first metal layer (206). The method further comprises implanting (152) nitrogen in the NMOS region (210) of substrate (202) and converting (154) a first portion of the first metal layer (206) into a metal oxide layer (220) and converting a second portion of the first metal layer (206) into metal nitride layer (218). The method further comprises forming (156) the NMOS gate (226) and the PMOS gate (228), where the NMOS gate (226) comprises a segment (234) of metal nitride layer (218) and the PMOS gate (228) comprises a segment (242) of the metal oxide layer (220).
摘要翻译：根据一个示例性实施例，用于将第一金属层（206）和第二金属层（208）集成在衬底（202）上以形成双金属NMOS栅极（226）和PMOS栅极（228）的方法包括沉积（150）在衬底（202）的NMOS区域（210）和PMOS区域（212）上形成层（204）。该方法还包括在介电层（204）上沉积（150）第一金属层（206）。该方法还包括在第一金属层（206）上沉积（150）第二金属层（208）。该方法进一步包括在衬底（202）的NMOS区域（210）中注入（152）氮并且将第一金属层（206）的第一部分转换（154）成金属氧化物层（220）并且将第二部分的第一金属层（206）进入金属氮化物层（218）。该方法还包括形成（156）NMOS栅极（226）和PMOS栅极（228），其中NMOS栅极（226）包括金属氮化物层（218）的片段（234），并且PMOS栅极（228）包括金属氧化物层（220）的区段（242）。

60. 发明申请

WO2005047561A1 CVD TANTALUM COMPOUNDS FOR FET GATE ELECTRODES 审中-公开
标题翻译：用于FET栅极电极的CVD TANTALUM化合物
公开(公告)号：WO2005047561A1
公开(公告)日：2005-05-26
申请号：PCT/EP2004/052927
申请日：2004-11-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , NARAYANAN, Vijay , MCFEELY, Fenton , MILKOVE, Keith, Raymond , YURKAS, John, Jacob , COPEL, Matthew, Warren , JAMISON, Paul, Charles , CARRUTHERS, Roy , CABRAL JNR, Cyril , SIKORSKI, Edmund , DUCH, Elizabeth , CALLEGARI, Alessandro , ZAFAR, Sufi , NAKAMURA, Kazuhito
发明人： NARAYANAN, Vijay , MCFEELY, Fenton , MILKOVE, Keith, Raymond , YURKAS, John, Jacob , COPEL, Matthew, Warren , JAMISON, Paul, Charles , CARRUTHERS, Roy , CABRAL JNR, Cyril , SIKORSKI, Edmund , DUCH, Elizabeth , CALLEGARI, Alessandro , ZAFAR, Sufi , NAKAMURA, Kazuhito
IPC分类号： C23C16/34
CPC分类号： C23C16/34 , H01L21/28088 , H01L21/823828 , H01L29/4966 , H01L29/78
摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO 2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta - N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta-N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.
摘要翻译：公开了用于场效应装置中的栅极材料的Ta和N的化合物，潜在地包括其它元素，电阻率低于约20mohmcm，并且N与Ta的元素比大于约0.9。这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下对含SiO 2的电介质层和高k电介质层是稳定的，功函数接近n型Si的功函数。金属Ta-N化合物通过化学气相沉积法使用烷基亚氨基三（二烷基酰氨基）Ta物质如叔戊酰亚氨基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。用TaN或TaSiN处理的器件显示出接近理想的特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式