专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

WO01037058A1 AUTOMATION DEVICE AND UPDATING METHOD 审中-公开
标题翻译：自动化装置及方法AUFDAT-
公开(公告)号：WO01037058A1
公开(公告)日：2001-05-25
申请号：PCT/DE2000/004002
申请日：2000-11-14
IPC分类号： G06F11/20 , G05B9/03 , G05B19/042 , G05B19/408 , G06F9/46 , G05B19/414
CPC分类号： G05B19/0428 , G05B19/408 , G05B2219/24182 , G05B2219/24186 , G05B2219/24187 , G06F11/1658 , G06F11/2038
摘要： The invention relates to an automation device (AG) comprising a task-oriented user program whose memory contents (M) are to be transmitted to a redundant automation device (AG') without interrupting operation. After the conventional transfer of a basic data stock, the transfer of intermediately modified data is effected by means of updating tasks (T1A, T2A) that are assigned to the individual tasks (T1, T2), whereby these updating tasks transmit only the part (M1, M2) of the memory contents (M) that is accessed by the respective tasks (T1, T2).
摘要翻译：它是用一个面向任务的应用程序的自动化装置（AG）指定，存储器的内容（M），而无需中断操作到冗余可编程控制器（AG“）被发送。根据转印的基本数据库的一个传统的传送通过的各个任务的装置（T1，T2）中进行与更新任务（T1A，T2A），这些仅那些段（M1，M2）发送存储器内容（M），其各自的相关联之间随时间变化的数据任务（T1，T2）的访问。

52. 发明申请

WO00060463A1 BACKGROUND SYNCHRONIZATION FOR FAULT-TOLERANT SYSTEMS 审中-公开
标题翻译：用于容错系统的背景同步
公开(公告)号：WO00060463A1
公开(公告)日：2000-10-12
申请号：PCT/US2000/008940
申请日：2000-04-05
IPC分类号： G06F11/14 , G06F11/20
CPC分类号： G06F11/1658 , G06F11/1461 , G06F11/1466 , G06F11/2071 , G06F11/2097
摘要： An inactive memory is synchronized with an active memory in a fault-tolerant computer system that includes an active processor. Data is copied from the active memory to the inactive memory using a background process that permits the active processor to perform normal operations while the copying is proceeding. Regions of the active memory in which changes are made are tracked while the copying is proceeding, and, after copying is complete, a determination is made as to whether data from the regions of the active memory in which changes were made can be copied to the inactive memory within a predetermined time period using a foreground process that prevents the active processor from performing normal operations. If the data can be copied to the inactive memory within the predetermined time period using the foreground process, the data is copied to the inactive memory using the foreground process. If the data cannot be copied to the inactive memory within the predetermined time period using the foreground process, the copying, tracking, and determining are repeated for the regions of the active memory in which changes were made.
摘要翻译：非活动存储器与包含有效处理器的容错计算机系统中的活动存储器同步。使用后台进程将数据从活动存储器复制到非活动存储器，后台进程允许活动处理器在复制进行期间执行正常操作。在进行复制的同时跟踪进行改变的活动存储器的区域，并且在复制完成之后，确定来自进行了改变的活动存储器的区域的数据是否可以复制到在预定时间段内使用防止活动处理器执行正常操作的前台进程的非活动存储器。如果使用前景处理在预定时间段内可以将数据复制到非活动存储器，则使用前台处理将数据复制到非活动存储器。如果使用前景处理在预定时间段内无法将数据复制到非活动存储器，则对进行了改变的活动存储器的区域重复复制，跟踪和确定。

53. 发明申请

WO9966406A9 PROCESSOR BRIDGE WITH POSTED WRITE BUFFER 审中-公开
标题翻译：具有位置写缓冲区的处理器桥
公开(公告)号：WO9966406A9
公开(公告)日：2000-04-06
申请号：PCT/US9912606
申请日：1999-06-04
申请人： SUN MICROSYSTEMS INC
发明人： GARNETT PAUL J , ROWLINSON STEPHEN , OYELAKIN FEMI A
IPC分类号： G06F11/18 , G06F11/16 , G06F13/36 , G06F13/40 , G06F13/28
CPC分类号： G06F11/1641 , G06F11/1625 , G06F11/165 , G06F11/1658 , G06F13/4027
摘要： A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. The bridge also includes a memory subsystem and a bridge control mechanism. The bridge control mechanism is operable to monitor operation of the first and second processing sets in a combined, lockstep, operating mode and to be responsive to detection of a lockstep error to cause the bridge to be operable in an error mode in which write accesses initiated by the processor sets are buffered in a bridge buffer pending resolution of the error mode. A respective buffer region is provided for each processing set. In an initial error mode, any complete device write accesses initiated by the processing sets are stored in a posted write buffer. Where data is in transit through the bridge on entry to the error mode, the data is diverted to one or more disconnect registers. The bridge control mechanism is operable to permit read access to the posted write buffers and the disconnect registers by the processing sets to enable recovery from the error mode.
摘要翻译：用于多处理器系统的桥接器包括用于连接到第一处理集合的I / O总线，第二处理集合的I / O总线和设备总线的总线接口。该桥还包括一个内存子系统和一个桥接控制机制。桥接控制机制可操作以在组合的，锁步骤的操作模式中监视第一和第二处理集合的操作，并且响应于检测到锁步错误，以使桥可以以写入存取开始的错误模式工作由处理器组缓冲在桥接缓冲器中等待解决错误模式。为每个处理集提供相应的缓冲区。在初始错误模式下，由处理集发起的任何完整的设备写访问都存储在已发布的写缓冲区中。数据在进入错误模式时通过桥接器传输，数据转移到一个或多个断开连接寄存器。桥接控制机制可操作以允许通过处理集读取对已发布的写入缓冲器和断开寄存器的读取，以使得能够从错误模式恢复。

54. 发明申请

WO99066408A1 SYNCHRONIZATION OF PROCESSORS IN A FAULT TOLERANT MULTI-PROCESSOR SYSTEM 审中-公开
标题翻译：处理器在容错多处理器系统中的同步化
公开(公告)号：WO99066408A1
公开(公告)日：1999-12-23
申请号：PCT/SE1999/001110
申请日：1999-06-18
IPC分类号： G06F11/18 , G06F11/16 , G06F11/20 , G06F15/177 , G06F15/163
CPC分类号： G06F11/1658
摘要： A method and system are described for synchronizing a first processor (10) unit with a second processor unit (20) in a fault tolerant system comprising a plurality of processing units where all processing units are executing the same processes in synchronization. The invention is readily adapted to a system of loosely coupled processing units with a low bandwidth communication channel (16) coupled between the processing units.
摘要翻译：描述了一种方法和系统，用于在包括多个处理单元的容错系统中使第一处理器（10）单元与第二处理器单元（20）同步，其中所有处理单元同步地执行相同的进程。本发明容易适用于具有耦合在处理单元之间的低带宽通信信道（16）的松耦合处理单元的系统。

55. 发明申请

WO99066404A1 MULTI-PROCESSOR SYSTEM BRIDGE WITH CONTROLLED ACCESS 审中-公开
标题翻译：具有控制访问的多处理器系统桥
公开(公告)号：WO99066404A1
公开(公告)日：1999-12-23
申请号：PCT/US1999/012431
申请日：1999-06-03
IPC分类号： G06F11/18 , G06F11/00 , G06F11/16 , G06F11/22 , G06F13/36 , G06F13/40 , G06F13/28
CPC分类号： G06F11/1658 , G06F11/004 , G06F11/1625 , G06F11/2268 , G06F13/4027
摘要： A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. It also comprises a bridge control mechanism configured to be operable, in an operational mode to permit access by at least one of the first and second processing sets to bridge resources and to the device bus and, in an error mode, to prevent access by the processing sets to the device bus and to permit restricted access to at least one of the processing sets to at least predetermined bridge resources. By providing restricted access to selected parameters held in the bridge during an error mode, the bridge can act as a secure repository for information which can be used by the processing sets to investigate the error and hopefully to recover therefrom, while preventing I/O devices connected to device bus from being corrupted by a faulty processing set. Storage in the bridge provides for buffering data pending resolution of the error.
摘要翻译：用于多处理器系统的桥接器包括用于连接到第一处理集合的I / O总线，第二处理集合的I / O总线和设备总线的总线接口。它还包括桥接控制机构，其被配置为在操作模式下可操作以允许第一和第二处理集合中的至少一个访问以桥接资源和设备总线，并且在错误模式下，以防止由处理集合到设备总线并且允许对至少一个处理集合的限制访问到至少预定的网桥资源。通过在错误模式期间提供对桥中保持的选定参数的受限访问，桥可以充当用于信息的安全存储库，以便处理集可以使用这些信息来调查错误并希望从中恢复错误，同时防止I / O设备连接到设备总线被错误的处理集损坏。桥梁中的存储提供缓冲数据，以解决错误。

56. 发明申请

WO99026133A2 FAULT RESILIENT/FAULT TOLERANT COMPUTING 审中-公开
标题翻译：故障恢复/故障计算
公开(公告)号：WO99026133A2
公开(公告)日：1999-05-27
申请号：PCT/US1998/024378
申请日：1998-11-13
IPC分类号： G06F11/18 , G06F11/16 , G06F15/177 , G06F9/00
CPC分类号： G06F11/1633 , G06F11/1641 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/1687 , G06F11/1691
摘要： A fault tolerant/fault resilient computer system includes at least two compute elements connected to at least one controller. Each compute element has clocks that operate asynchronously to clocks of the other compute elements. The compute elements operate in a first mode in which the compute elements each execute a first stream of instructions in emulated clock lockstep, and in a second mode in which the compute elements each execute a second stream of instructions in instruction lockstep. Each compute element may be a multi-processor compute element.
摘要翻译：容错/故障恢复计算机系统包括连接到至少一个控制器的至少两个计算元件。每个计算元件具有与其他计算元素的时钟异步运行的时钟。计算元件以第一模式操作，其中计算元件各自在仿真时钟锁步骤中执行指令的第一流，并且在第二模式中，计算元件在指令锁定步骤中每个执行第二指令流。每个计算元件可以是多处理器计算元件。

57. 发明申请

WO9722046A3 REMOTE CHECKPOINT MEMORY SYSTEM AND PROTOCOL FOR FAULT-TOLERANT COMPUTER SYSTEM 审中-公开
标题翻译：远程检测点记忆系统和容错计算机系统协议
公开(公告)号：WO9722046A3
公开(公告)日：1997-09-25
申请号：PCT/US9618980
申请日：1996-11-27
申请人： SEQUOIA SYSTEMS INC
发明人： STIFFLER JACK J
IPC分类号： G06F11/14 , G06F11/20 , G06F
CPC分类号： G06F11/1658 , G06F11/1407
摘要： A mechanism for maintaining a consistent, periodically updated state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In this invention, a first computer includes a processor and input/ouput elements connected to a main memory subsystem including a primary element. A second computer has a remote checkpoint memory element, which may include one or more buffer memories and a shadowy memory, which is connected to the main memory subsystem of the first computer. During normal processing, an image of data written to the primary memory element is captured by the remote checkpoint memory element. When a new checkpoint is desired (thereby establishing a consistent state in main memory to which all executing applications can safely return following a fault), the data previously captured is used to establish a new checkpointed state in the second computer. In case of failure of the first computer, the second computer can be restarted to operate from the last checkpoint established for the first computer. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation. 00000
摘要翻译：提供了一种用于在主存储器中维持一致的周期性更新状态而不限制正常计算机操作的机制，从而使得计算机系统能够在不损失数据或处理连续性的情况下从故障中恢复。在本发明中，第一计算机包括处理器和连接到包括主要元件的主存储器子系统的输入/输出元件。第二计算机具有远程检查点存储元件，其可以包括连接到第一计算机的主存储器子系统的一个或多个缓冲存储器和阴影存储器。在正常处理期间，写入主存储元件的数据的图像由远程检查点存储元件捕获。当需要新的检查点（从而在主存储器中建立一致的状态，所有执行的应用程序可以在故障之后安全地返回），先前捕获的数据被用于在第二计算机中建立新的检查点状态。在第一台计算机发生故障的情况下，可以从为第一台计算机建立的最后一个检查点重新启动第二台计算机。该结构和协议可以保证主存储器中的一致状态，从而实现容错操作。 00000

58. 发明申请

WO1997022046A2 REMOTE CHECKPOINT MEMORY SYSTEM AND PROTOCOL FOR FAULT-TOLERANT COMPUTER SYSTEM 审中-公开
标题翻译：远程检测点记忆系统和容错计算机系统协议
公开(公告)号：WO1997022046A2
公开(公告)日：1997-06-19
申请号：PCT/US1996018980
申请日：1996-11-27
申请人： SEQUOIA SYSTEMS, INC.
发明人： SEQUOIA SYSTEMS, INC. , STIFFLER, Jack, J.
IPC分类号： G06F00/00
CPC分类号： G06F11/1658 , G06F11/1407
摘要： A mechanism for maintaining a consistent, periodically updated state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In this invention, a first computer includes a processor and input/ouput elements connected to a main memory subsystem including a primary element. A second computer has a remote checkpoint memory element, which may include one or more buffer memories and a shadowy memory, which is connected to the main memory subsystem of the first computer. During normal processing, an image of data written to the primary memory element is captured by the remote checkpoint memory element. When a new checkpoint is desired (thereby establishing a consistent state in main memory to which all executing applications can safely return following a fault), the data previously captured is used to establish a new checkpointed state in the second computer. In case of failure of the first computer, the second computer can be restarted to operate from the last checkpoint established for the first computer. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.
摘要翻译：提供了一种用于在主存储器中维持一致的周期性更新状态而不限制正常计算机操作的机制，从而使得计算机系统能够在不损失数据或处理连续性的情况下从故障中恢复。在本发明中，第一计算机包括处理器和连接到包括主要元件的主存储器子系统的输入/输出元件。第二计算机具有远程检查点存储元件，其可以包括连接到第一计算机的主存储器子系统的一个或多个缓冲存储器和阴影存储器。在正常处理期间，写入主存储元件的数据的图像由远程检查点存储元件捕获。当需要新的检查点（从而在主存储器中建立一致的状态，所有执行的应用程序可以在故障之后安全地返回），先前捕获的数据被用于在第二计算机中建立新的检查点状态。在第一台计算机发生故障的情况下，可以从为第一台计算机建立的最后一个检查点重新启动第二台计算机。该结构和协议可以保证主存储器中的一致状态，从而实现容错操作。

59. 发明申请

WO1997004390A1 TRANSACTION CLASH MANAGEMENT IN A DISCONNECTABLE COMPUTER AND NETWORK 审中-公开
标题翻译：不连接的计算机和网络中的事务处理
公开(公告)号：WO1997004390A1
公开(公告)日：1997-02-06
申请号：PCT/US1996011902
申请日：1996-07-18
申请人： NOVELL, INC. , FALLS, Patrick, T. , COLLINS, Brian, J. , DRAPER, Stephen, P., W.
发明人： NOVELL, INC.
IPC分类号： G06F11/14
CPC分类号： G06F9/466 , G06F11/1658 , G06F11/2094 , G06F17/30575
摘要： A method and apparatus are disclosed for detecting and handling clashes that may occur when transactions performed on disconnected replicas of a database are merged after the computers carrying the replicas are reconnected. A variety of clashes are addressed, including those which arise from inconsistent add, remove, move, and modify operations. Transient clashes that would resolve themselves without significant intervention are distinguished from persistent clashes. Log patching, regression, key modification, duplication, and a variety of other tools for handling the clashes are described.
摘要翻译：公开了一种用于检测和处理在重新连接了携带副本的计算机之后合并在数据库的断开的副本上执行的事务时可能发生的冲突的方法和装置。处理各种冲突，包括由不一致的添加，删除，移动和修改操作引起的冲突。在没有重大干预的情况下解决自己的瞬间冲突与持续的冲突不同。描述日志修补，回归，关键修改，复制以及处理冲突的各种其他工具。

60. 发明申请

WO1995015529A1 FAULT RESILIENT/FAULT TOLERANT COMPUTING 审中-公开
标题翻译：故障恢复/故障计算
公开(公告)号：WO1995015529A1
公开(公告)日：1995-06-08
申请号：PCT/US1994013350
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： MARATHON TECHNOLOGIES CORPORATION , BISSETT, Thomas, D. , FIORENTINO, Richard, D. , GLORIOSO, Robert, M. , MCCAULEY, Diane, T. , MCCOLLUM, James, D. , TREMBLAY, Glenn, A. , TROIANI, Mario
IPC分类号： G06F15/16
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).
摘要翻译：一种同步至少两个计算元件（CE1，CE2）的方法，每个计算元件（CE1，CE2）具有与其他计算元件的时钟异步工作的时钟，包括从一组信号中选择一个或多个指定为元时间信号的信号，计算元件（CE1，CE2），监视计算元件（CE1，CE2），以通过计算元件（CE1）之一检测所选信号的产生，等待其他计算元件（CE2）产生所选信号，向每个计算元件发送等价的时间更新，以及基于时间更新来更新计算元件（CE1，CE2）的时钟。在本发明的第二方面中，通过将第一处理器指定为计算元件（204），指定作为控制器的第二处理器（202）来连接计算元件（204）来产生故障回复或容忍的计算机（200））和所述控制器（202）以产生模块对，并且连接至少两个模块对以产生故障恢复或容错计算机（200）。计算机（200）的每个计算元件（202,204）以与其它计算元件（202,204）相同的周期数执行所有指令。计算机系统包括一个或多个控制器（202）和至少两个计算元件（204）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式