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    • 2. 发明申请
    • PROCESSOR BRIDGE WITH POSTED WRITE BUFFER
    • 具有位置写缓冲区的处理器桥
    • WO9966406A9
    • 2000-04-06
    • PCT/US9912606
    • 1999-06-04
    • SUN MICROSYSTEMS INC
    • GARNETT PAUL JROWLINSON STEPHENOYELAKIN FEMI A
    • G06F11/18G06F11/16G06F13/36G06F13/40G06F13/28
    • G06F11/1641G06F11/1625G06F11/165G06F11/1658G06F13/4027
    • A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. The bridge also includes a memory subsystem and a bridge control mechanism. The bridge control mechanism is operable to monitor operation of the first and second processing sets in a combined, lockstep, operating mode and to be responsive to detection of a lockstep error to cause the bridge to be operable in an error mode in which write accesses initiated by the processor sets are buffered in a bridge buffer pending resolution of the error mode. A respective buffer region is provided for each processing set. In an initial error mode, any complete device write accesses initiated by the processing sets are stored in a posted write buffer. Where data is in transit through the bridge on entry to the error mode, the data is diverted to one or more disconnect registers. The bridge control mechanism is operable to permit read access to the posted write buffers and the disconnect registers by the processing sets to enable recovery from the error mode.
    • 用于多处理器系统的桥接器包括用于连接到第一处理集合的I / O总线,第二处理集合的I / O总线和设备总线的总线接口。 该桥还包括一个内存子系统和一个桥接控制机制。 桥接控制机制可操作以在组合的,锁步骤的操作模式中监视第一和第二处理集合的操作,并且响应于检测到锁步错误,以使桥可以以写入存取开始的错误模式工作 由处理器组缓冲在桥接缓冲器中等待解决错误模式。 为每个处理集提供相应的缓冲区。 在初始错误模式下,由处理集发起的任何完整的设备写访问都存储在已发布的写缓冲区中。 数据在进入错误模式时通过桥接器传输,数据转移到一个或多个断开连接寄存器。 桥接控制机制可操作以允许通过处理集读取对已发布的写入缓冲器和断开寄存器的读取,以使得能够从错误模式恢复。
    • 4. 发明申请
    • RESOURCE CONTROL IN A COMPUTER SYSTEM
    • 计算机系统中的资源控制
    • WO9966416A3
    • 2001-12-13
    • PCT/US9912605
    • 1999-06-04
    • SUN MICROSYSTEMS INC
    • ROWLINSON STEPHENOYELAKIN FEMI AWILLIAMS EMRYS JGARNETT PAUL J
    • G06F13/14G06F11/18G06F13/36G06F13/40
    • G06F13/4027
    • A bridge for a computer system comprising at least a first processing set and a second processing set each connected to the bridge via an I/O bus. A resource control mechanism in the bridge comprises: an interface for exchanging signals with one or more resource slots of a device bus that is capable of being connected to the bridge, each of the resource slots being capable of communicating with a system resource; and a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system.
    • 一种用于计算机系统的桥,包括至少第一处理集和第二处理集合,每个第一处理集合和第二处理集合经由I / O总线连接到所述网桥。 桥中的资源控制机制包括:用于与能够连接到网桥的设备总线的一个或多个资源时隙交换信号的接口,每个资源槽能够与系统资源进行通信; 以及与每个系统资源相关联的寄存器,所述寄存器具有指示相关系统资源的操作状态的可切换标记,所述控制机制可用于将信号引导到和/或从所述计算机系统的相应系统资源。