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41. 发明申请

WO2015089314A1 COMPUTER PROCESSOR EMPLOYING OPERAND DATA WITH ASSOCIATED META-DATA 审中-公开
标题翻译：计算机处理器使用相关的元数据操作数据
公开(公告)号：WO2015089314A1
公开(公告)日：2015-06-18
申请号：PCT/US2014/069811
申请日：2014-12-11
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David , YOST, David, Arthur , MIROLO, Sebastien Paul, Maurice
IPC分类号： G06F9/38
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/3016 , G06F9/30163 , G06F9/30192 , G06F9/3859 , G06F9/3865 , G06F11/0721 , G06F11/0772 , G06F12/14
摘要： A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.
摘要翻译：提供了一种计算机处理器，其采用将操作数数据值和相关联的元数据存储为单一操作数数据元素的多个操作数存储元件以及执行产生和访问存储在其中的单一操作数数据元素的操作的至少一个功能单元多个操作数存储元件。与作为单一操作数数据元素的一部分的给定操作数数据值相关联的元数据可以指定单一操作数数据元素（例如，向量或标量），元素宽度和浮点错误标志的类型。元数据也可用于定义特殊的操作数数据值（例如非结果和无）。元数据在优化执行中非常有用，例如在推测和矢量化SIMD操作中。计算机处理器还可以支持用于优化矢量化SIMD操作的执行的许多特定向量操作。

42. 发明申请

WO2014151043A1 A METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE 审中-公开
标题翻译：通过使用内部分布式标志架构来模拟客户中心标志架构的方法
公开(公告)号：WO2014151043A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/024828
申请日：2014-03-12
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30094 , G06F9/3012 , G06F9/30174 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3863 , G06F9/3893
摘要： A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and using a distributed flag architecture to emulate a centralized flag architecture for the emulation of guest instruction execution.
摘要翻译：一种通过使用本地分布式标志体系结构模拟客户集中式标志体系结构的方法。该方法包括使用全局前端接收输入指令序列; 将指令分组以形成指令块，其中每个指令块包括两个半块; 根据调度器调度指令块的指令执行; 并使用分布式标志架构来模拟用于仿真客户指令执行的集中式标志架构。

43. 发明申请

WO2014090091A1 TRACKING MULTIPLE CONDITIONS IN A GENERAL PURPOSE REGISTER AND INSTRUCTION THEREFOR 审中-公开
标题翻译：跟踪一般用途注册表中的多个条件及其指示
公开(公告)号：WO2014090091A1
公开(公告)日：2014-06-19
申请号：PCT/CN2013/088085
申请日：2013-11-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) CO., LIMITED
发明人： GREINER, Dan F. , GSCHWIND, Michael K.
IPC分类号： G06F17/30
CPC分类号： G06F9/30043 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/3836 , G06F9/384
摘要： An operate-and-insert instruction of a program, when executed performs an operation based on one or more operands, results of an instruction specified test of the operation performed are stored in an instruction specified location of an instruction specified general register. The instruction specified general register is therefore able to hold results of many operate-and-insert instructions. The program can then use non-branch type instructions to evaluate conditions saved in the register, thus avoiding the performance penalty of branch instructions.
摘要翻译：程序的操作和插入指令在执行时执行基于一个或多个操作数的操作，所执行的操作的指令测试结果被存储在指令通用寄存器的指令指定位置。因此，指定通用寄存器的指令能够保存许多操作和插入指令的结果。然后，程序可以使用非分支类型的指令来评估寄存器中保存的条件，从而避免分支指令的性能损失。

44. 发明申请

WO2013101119A1 METHOD AND APPARATUS FOR CONTROLLING A MXCSR 审中-公开
标题翻译：用于控制MXCSR的方法和装置
公开(公告)号：WO2013101119A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067957
申请日：2011-12-29
申请人： INTEL CORPORATION , MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
发明人： MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
IPC分类号： G06F15/76 , G06F9/30 , G06F9/44
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.
摘要翻译：公开了一种通常涉及控制多媒体扩展控制和状态寄存器（MXCSR）的装置和方法。处理器核心可以包括用于执行算术功能的浮点单元（FPU）以及为FPU提供控制位的多媒体扩展控制寄存器（MXCR）。此外，优化器可以用于从多个SPEC_MXSR中选择推测性多媒体扩展状态寄存器（SPEC_MXSR），以基于指令来更新多媒体扩展状态寄存器（MXSR）。

45. 发明申请

WO2013095648A1 THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS 审中-公开
标题翻译：三个输入操作向量添加指令，不提供用于CRYPTOAPHAPH应用的算术标记
公开(公告)号：WO2013095648A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067230
申请日：2011-12-23
申请人： INTEL CORPORATION , FEGHALI, Wajdi K. , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , WOLRICH, Gilbert M. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G.
发明人： FEGHALI, Wajdi K. , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , WOLRICH, Gilbert M. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G.
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30181
摘要： A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport.
摘要翻译：描述了一种方法，其包括在半导体芯片上实现的指令执行流水线内执行以下操作：通过执行单个指令对三个输入向量操作数相加; 并且，即使求和的结果产生比设计用于传送求和的电路更多的位能够传输，也不会提高任何算术标记。

46. 发明申请

WO2013095259A1 VECTOR EXECUTION UNIT FOR DIGITAL SIGNAL PROCESSOR 审中-公开
标题翻译：用于数字信号处理器的矢量执行单元
公开(公告)号：WO2013095259A1
公开(公告)日：2013-06-27
申请号：PCT/SE2012/051322
申请日：2012-11-28
申请人： MEDIATEK SWEDEN AB
发明人： NILSSON, Anders , TELL, Eric
IPC分类号： G06F9/38 , G06F9/30 , G06F15/80
CPC分类号： G06F9/30145 , G06F9/30021 , G06F9/30094 , G06F9/3887 , G06F15/78 , G06F15/8084
摘要： A vector execution unit for use in a digital signal processor enables a new set of instructions. The unit comprises a first input port for receiving at least a first input data vector, an instruction decoder, a vector output port, and least one data-path. The instruction decoding unit is arranged to control the data-path to perform a comparison related to the first input data vector, and the processor comprises an integer port arranged to output the result of the comparison in the form of a decision vector to a memory unit or a functional unit in the digital signal processor. Alternatively or in addition, the integer port is also arranged to receive a decision vector of integer data, and the instruction decoding unit is arranged to control the data-path to process the first input data in dependence of the value of the integer data.
摘要翻译：用于数字信号处理器的矢量执行单元能够实现新的一组指令。该单元包括用于接收至少第一输入数据向量，指令解码器，向量输出端口和至少一个数据路径的第一输入端口。所述指令解码单元被配置为控制所述数据路径以执行与所述第一输入数据向量相关的比较，并且所述处理器包括整数端口，所述整数端口被布置为将所述比较结果以决策向量的形式输出到存储器单元或数字信号处理器中的功能单元。或者或另外，整数端口还被布置为接收整数数据的判决向量，并且指令解码单元被布置为根据整数数据的值来控制数据路径来处理第一输入数据。

47. 发明申请

WO2013074074A1 FLAG NON-MODIFICATION EXTENSION FOR ISA INSTRUCTIONS USING PREFIXES 审中-公开
标题翻译：标志使用前缀的ISA指令的非修改扩展
公开(公告)号：WO2013074074A1
公开(公告)日：2013-05-23
申请号：PCT/US2011/060645
申请日：2011-11-14
申请人： INTEL CORPORATION , COMBS, Jonathan D. , BRANDT, Jason W. , VALENTINE, Robert
发明人： COMBS, Jonathan D. , BRANDT, Jason W. , VALENTINE, Robert
IPC分类号： G06F9/30 , G06F9/06
CPC分类号： G06F9/30145 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
摘要翻译：在一个实施例中，处理器包括用于接收和解码具有前缀和操作码的指令的指令解码器，基于操作码执行指令的执行单元和用于防止执行单元修改标志寄存器的标志修改覆盖逻辑的处理器基于指令的前缀。

48. 发明申请

WO2012098435A1 INTEGRATED CIRCUIT DEVICE AND METHOD FOR CALCULATING A PREDICATE VALUE 审中-公开
标题翻译：集成电路设备和计算预测值的方法
公开(公告)号：WO2012098435A1
公开(公告)日：2012-07-26
申请号：PCT/IB2011/050275
申请日：2011-01-21
申请人： FREESCALE SEMICONDUCTOR, INC. , PELED, Yuval , BARAK, Itzhak , ROZENBERG, Idan , SCHUPPER, Doron , VASKEVICH, Lev
发明人： PELED, Yuval , BARAK, Itzhak , ROZENBERG, Idan , SCHUPPER, Doron , VASKEVICH, Lev
IPC分类号： G06F7/57 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/57 , G06F9/30029 , G06F9/30072 , G06F9/30094
摘要： An integrated circuit device (105) comprises at least one instruction processing module (100) arranged to perform branch predication. The at least one instruction processing module (100) comprises at least one predicate calculation module (150) arranged to receive as an input at least one result vector (220) for a predicate function and at least one conditional parameter value therefor (230), and output a predicate result value (240) from the at least one result vector (220) based at least partly on the at least one received conditional parameter value (230).
摘要翻译：集成电路装置（105）包括布置成执行分支预测的至少一个指令处理模块（100）。所述至少一个指令处理模块（100）包括至少一个谓词计算模块（150），其被布置为接收用于谓词函数的至少一个结果向量（220）作为输入，以及至少一个用于其的条件参数值（230）并且至少部分地基于所述至少一个接收到的条件参数值（230）从所述至少一个结果向量（220）输出谓词结果值（240）。

49. 发明申请

WO2011147483A1 DECIMAL FLOATING-POINT QUANTUM EXCEPTION DETECTION 审中-公开
标题翻译：十进制浮点量子除法检测
公开(公告)号：WO2011147483A1
公开(公告)日：2011-12-01
申请号：PCT/EP2010/067054
申请日：2010-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , SCHWARZ, Eric, Mark , YEH, Phil , COWLISHAW, Michael, Frederic , MUELLER, Silvia, Melitta
发明人： SCHWARZ, Eric, Mark , YEH, Phil , COWLISHAW, Michael, Frederic , MUELLER, Silvia, Melitta
IPC分类号： G06F9/302 , G06F7/491 , G06F7/499 , G06F9/38
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译：用于检测十进制浮点数据处理异常的系统和方法。一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。确定十进制浮点结果是否不能保持优选的量子。优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。

50. 发明申请

WO2009087158A4 COMPARE AND BRANCH FACILITY AND INSTRUCTION THEREFORE 审中-公开
标题翻译：比较和分支机构及其说明
公开(公告)号：WO2009087158A4
公开(公告)日：2009-11-12
申请号：PCT/EP2009050105
申请日：2009-01-07
申请人： IBM , IBM UK , GREINER DAN , SLEGEL TIMOTHY
发明人： GREINER DAN , SLEGEL TIMOTHY
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/30094 , G06F9/30167
摘要： An atomic compare and branch instruction is executed that combines the function of a compare instruction having an option field with a conditional branch or jump instruction such that condition codes are preserved rather than setting condition codes to a value representative of the compare results. One comparand is obtained from any one of a memory location or an immediate field and the other comparand is obtained from a register field.
摘要翻译：执行原子比较和分支指令，其将具有选项字段的比较指令的功能与条件分支或跳转指令相组合，以便保存条件码而不是将条件码设置为表示比较结果的值。一个比较数是从存储位置或立即数字段中的任何一个获得的，而另一个比较数是从寄存器字段获得的。

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