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1. 发明申请

WO2013101078A8 SUPPORT FOR SPECULATIVE OWNERSHIP WITHOUT DATA 审中-公开
标题翻译：支持无数据的统计所有权
公开(公告)号：WO2013101078A8
公开(公告)日：2013-09-06
申请号：PCT/US2011067865
申请日：2011-12-29
申请人： INTEL CORP , GIBERT CODINA ENRIC , LATORRE FERNANDO , CODINA JOSEP M , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MEYREM , KOTSELIDIS CHRISTOS E , LOPEZ PEDRO , LUPON MARC , MADRILES CARLOS , MAGKLIS GRIGORIOS , MARCUELLO PEDRO , MARTINEZ VICENTE ALEJANDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , STAVROU KYRIAKOS A , TOURNAVITIS GEORGIOS , XEKALAKIS POLYCHRONIS
发明人： GIBERT CODINA ENRIC , LATORRE FERNANDO , CODINA JOSEP M , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MEYREM , KOTSELIDIS CHRISTOS E , LOPEZ PEDRO , LUPON MARC , MADRILES CARLOS , MAGKLIS GRIGORIOS , MARCUELLO PEDRO , MARTINEZ VICENTE ALEJANDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , STAVROU KYRIAKOS A , TOURNAVITIS GEORGIOS , XEKALAKIS POLYCHRONIS
IPC分类号： G06F9/06 , G06F12/08
CPC分类号： G06F12/0815 , G06F2212/507
摘要： Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.
摘要翻译：描述了用于为多核处理器提供增强的高速缓存一致性协议的技术，所述多核处理器包括用于高速缓冲存储器的一部分的无数据的所有权投标请求（SRFOWD）。使用SRFOWD，可以仅提供确认消息作为请求内核的答案。受影响的缓存行的内容不需要作为答案的一部分。增强的高速缓存一致性协议可以确保在请求核心的错误配置的情况下存在当前高速缓存行的有效副本。因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。如果请求的核心的猜测证明是正确的，则可以丢弃该高速缓存行的旧内容。否则，在请求核心发生错误的情况下，可以将高速缓存行的旧内容设置回有效状态。

2. 发明申请

WO2014154917A1 MECANISMO PARA FACILITAR LA FUSIÓN DINÁMICA Y EFICAZ DE INSTRUCCIONES INFORMÁTICAS EN PROGRAMAS DE SOFTWARE 审中-公开
标题翻译：促进软件程序中计算机指令的动态和有效协调的机制
公开(公告)号：WO2014154917A1
公开(公告)日：2014-10-02
申请号：PCT/ES2013/070209
申请日：2013-03-27
申请人： INTEL CORPORATION , LUPON, Marc
发明人： LUPON, Marc , MARTINEZ, Raul , CODINA, Enric Gibert , STAVROU, Kyriakos A. , MAGKLIS, Grigorios , SAMUDRALA, Sridhar
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/4432 , G06F8/4434 , G06F8/4441 , Y02D10/41
摘要： Se describe un mecanismo para facilitar la fusión dinámica y eficaz de instrucciones informáticas, según una realización. Un procedimiento de realizaciones, según lo descrito en la presente memoria, incluye monitorizar un programa de software para una región de programa con instrucciones candidatas a la fusión, para una operación de fusión en un sistema informático; evaluar si la macro-operación de las instrucciones candidatas es o no valiosa para el programa de software; y realizar la operación de fusión si se evalúa que es valiosa.
摘要翻译：本发明涉及一种用于促进根据实施例的计算机指令的动态和有效合并的机制。根据本文档中描述的本发明的方法包括：为计算机系统中的合并操作监视用于合并的候选指令的程序区域的软件程序; 评估候选指令的宏观操作是否对软件程序有益; 如果评估为有益的话，执行合并操作。

3. 发明申请

WO2013101121A1 MANAGED INSTRUCTION CACHE PREFETCHING 审中-公开
标题翻译：管理指令高速缓存
公开(公告)号：WO2013101121A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067964
申请日：2011-12-29
申请人： INTEL CORPORATION , STAVROU, Kyriakos A. , GIBERT CODINA, Enric , CODINA, Josep M. , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , LUPON, Marc , MADRILES, Carlos , MAGKLIS, Grigorios , MARCUELLO, Pedro , MARTINEZ VICENTE, Alejandro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
发明人： STAVROU, Kyriakos A. , GIBERT CODINA, Enric , CODINA, Josep M. , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , LUPON, Marc , MADRILES, Carlos , MAGKLIS, Grigorios , MARCUELLO, Pedro , MARTINEZ VICENTE, Alejandro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30047 , G06F9/3017 , G06F9/3802 , G06F9/3806 , G06F9/3848 , G06F12/0862 , G06F2212/452
摘要： Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
摘要翻译：公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。动态优化器可用于控制：识别公共指令高速缓存未命中并将预取引擎的预取指令插入指令高速缓存。

4. 发明申请

WO2013101078A1 SUPPORT FOR SPECULATIVE OWNERSHIP WITHOUT DATA 审中-公开
标题翻译：支持没有数据的定量所有权
公开(公告)号：WO2013101078A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067865
申请日：2011-12-29
申请人： INTEL CORPORATION , CONDIN, Enric, Gibert , LATORRE, Fernando , CODINA, Josep, M. , REQUENA, Crispin, Gomez , GONZALEZ, Antonio , HYUSEINOVA, Mirem, (meyrem) , KOTSELIDIS, Christos, E. , LOPEZ, Pedro , LUPON, Marc , MADRILES, Carlos , MAGKLIS, Grigorios , MARCUELLO, Pedro , MARTINEZ, Vicente Alejandro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos, A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
发明人： CONDIN, Enric, Gibert , LATORRE, Fernando , CODINA, Josep, M. , REQUENA, Crispin, Gomez , GONZALEZ, Antonio , HYUSEINOVA, Mirem, (meyrem) , KOTSELIDIS, Christos, E. , LOPEZ, Pedro , LUPON, Marc , MADRILES, Carlos , MAGKLIS, Grigorios , MARCUELLO, Pedro , MARTINEZ, Vicente Alejandro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos, A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
IPC分类号： G06F9/06 , G06F12/08
CPC分类号： G06F12/0815 , G06F2212/507
摘要： Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.
摘要翻译：描述了用于为多核处理器提供增强高速缓存一致性协议的技术，其包括针对高速缓存存储器的一部分的无数据所有权的推测请求（SRFOWD）。使用SRFOWD，只有确认消息可以作为对请求核心的答案提供。受影响的缓存行的内容不需要成为答案的一部分。增强的高速缓存一致性协议可以确保在请求核心的错误推测的情况下存在当前高速缓存行的有效副本。因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。如果请求核心的推测结果是正确的，那么高速缓存行的旧内容可能会被丢弃。否则，在发出请求核心的错误猜测的情况下，高速缓存行的旧内容可能会回到有效状态。

5. 发明申请

WO2013095569A1 METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION 审中-公开
标题翻译：方法，选择性执行委托指令的方法和系统
公开(公告)号：WO2013095569A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067021
申请日：2011-12-22
申请人： INTEL CORPORATION , CODINA, Enric Gibert , CODINA, Josep M. , LATORRE, Fernando , MARCUELLO, Pedro , LOPEZ, Pedro , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LUPON, Marc , GIMENO, Carlos Madriles , MAGKLIS, Grigorios , VICENTE, Alejandro Martinez , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
发明人： CODINA, Enric Gibert , CODINA, Josep M. , LATORRE, Fernando , MARCUELLO, Pedro , LOPEZ, Pedro , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LUPON, Marc , GIMENO, Carlos Madriles , MAGKLIS, Grigorios , VICENTE, Alejandro Martinez , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30087 , G06F9/30185 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.
摘要翻译：处理器确定是否执行提交动作的技术和机制。在一个实施例中，处理器执行操作以确定提交指令是否用于或然执行提交动作。在另一个实施例中，响应于确定提交指令用于提交动作的或然执行来评估处理器状态的一个或多个条件，其中执行评估以确定是否要执行由提交指令指示的提交动作。

6. 发明申请

WO2014004220A1 DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD 审中-公开
标题翻译：双重圆形组合浮点数乘法和加法
公开(公告)号：WO2014004220A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/046619
申请日：2013-06-19
申请人： INTEL CORPORATION , SAMUDRALA, Sridhar , MAGKLIS, Grigorios , LUPON, Marc , DITZEL, David R.
发明人： SAMUDRALA, Sridhar , MAGKLIS, Grigorios , LUPON, Marc , DITZEL, David R.
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F7/4876 , G06F7/483 , G06F7/485 , G06F7/4991 , G06F7/49915 , G06F7/5443 , G06F2207/4802
摘要： Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.
摘要翻译：公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数，基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。分别使用溢出检测选择最终结果。

7. 发明申请

WO2013101119A1 METHOD AND APPARATUS FOR CONTROLLING A MXCSR 审中-公开
标题翻译：用于控制MXCSR的方法和装置
公开(公告)号：WO2013101119A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067957
申请日：2011-12-29
申请人： INTEL CORPORATION , MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
发明人： MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
IPC分类号： G06F15/76 , G06F9/30 , G06F9/44
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.
摘要翻译：公开了一种通常涉及控制多媒体扩展控制和状态寄存器（MXCSR）的装置和方法。处理器核心可以包括用于执行算术功能的浮点单元（FPU）以及为FPU提供控制位的多媒体扩展控制寄存器（MXCR）。此外，优化器可以用于从多个SPEC_MXSR中选择推测性多媒体扩展状态寄存器（SPEC_MXSR），以基于指令来更新多媒体扩展状态寄存器（MXSR）。

8. 发明申请

WO2013101079A1 PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY 审中-公开
标题翻译：根据代码区域格式的软件执行情况分析异常事件
公开(公告)号：WO2013101079A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067866
申请日：2011-12-29
申请人： INTEL CORPORATION , MARTINEZ, Raul , GIBERT CODINA, Enric , LOPEZ, Pedro , TORRENTS LAPUERTA, Marti , XEKALAKIS, Polychronis , TOURNAVITIS, Georgios , STAVROU, Kyriakos, A. , PAVLOU, Demos , ORTEGA, Daniel , MARTINEZ VICENTE, Alejandro , MARCUELLO, Pedro , MAGKLIS, Grigorios , CODINA, Josep M. , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LUPON, Marc , MADRILES, Carlos
发明人： MARTINEZ, Raul , GIBERT CODINA, Enric , LOPEZ, Pedro , TORRENTS LAPUERTA, Marti , XEKALAKIS, Polychronis , TOURNAVITIS, Georgios , STAVROU, Kyriakos, A. , PAVLOU, Demos , ORTEGA, Daniel , MARTINEZ VICENTE, Alejandro , MARCUELLO, Pedro , MAGKLIS, Grigorios , CODINA, Josep M. , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LUPON, Marc , MADRILES, Carlos
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F11/3037 , G06F11/3409 , G06F11/3466 , G06F12/0862 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.
摘要翻译：硬件和软件的组合以代码区域粒度收集用于异步事件的简档数据。示例性实施例涉及收集在本质上是异步的预取事件的度量。使用几种替代技术之一来标识属于代码区域的指令，使得为指令设置配置文件位作为标记。预取数据块的每一行都被类似地标记。然后识别与正在收集并且由代码区域内的指令产生的简档数据相对应的事件。每次识别出不同类型的事件之一时，相应的计数器将被递增。在代码区域中执行指令之后，收集在计数器中累积的简档数据，并且重置计数器以与新的代码区域一起使用。

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