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31. 发明申请

WO2007047298A1 DESIGNER'S INTENT TOLERANCE BANDS FOR PROXIMITY CORRECTION AND CHECKING 审中-公开
标题翻译：设计师的意向修正和检查的公差容忍
公开(公告)号：WO2007047298A1
公开(公告)日：2007-04-26
申请号：PCT/US2006/039701
申请日：2006-10-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , MANSFIELD, Scott, M. , LIEBMANN, Lars, W. , GRAUR, Ioana , KRASNOPEROVA, Azalia
发明人： MANSFIELD, Scott, M. , LIEBMANN, Lars, W. , GRAUR, Ioana , KRASNOPEROVA, Azalia
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译：通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电子，重叠和可制造性约束特征对其他层的影响。该方法可以在用于在计算机系统上执行的计算机程序产品中实现。所得到的公差带可用于有效地将设计者的意图传达给平版印刷机，OPC工程师或掩模制造商或工具。

32. 发明申请

WO2007044557A2 SYSTEM, MASKS, AND METHODS FOR PHOTOMASKS OPTIMIZED WITH APPROXIMATE AND ACCURATE MERIT FUNCTIONS 审中-公开
标题翻译：具有近似和精准的功能优化的光子的系统，掩码和方法
公开(公告)号：WO2007044557A2
公开(公告)日：2007-04-19
申请号：PCT/US2006/039214
申请日：2006-10-06
申请人： LUMINESCENT TECHNOLOGIES, INC. , ABRAMS, Daniel, S. , PENG, Danping
发明人： ABRAMS, Daniel, S. , PENG, Danping
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： Photomask patterns are represented using contours defined by mask functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes "merit function" for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to rectilinear patterns), robustness against process variations, as well as restrictions imposed relating to practical and economic manufacturability of photomasks. An accurate, slower merit function may be used to determine adjustment parameters for a faster, approximate merit function. The faster merit function may be used for iteration and adjusted based on the adjustment parameters.
摘要翻译：光掩模图案使用由掩模功能定义的轮廓来表示。给定目标图案，轮廓被优化，使得定义的光掩模在光刻工艺中使用时，将晶片图案忠实地印刷到目标图案上。优化利用“优点功能”来编码光刻工艺的方面，与所得到的图案有关的偏好（例如对直线图案的限制），对工艺变化的鲁棒性以及与光掩模的实际和经济可制造性有关的限制。可以使用精确的较慢的优点函数来确定用于更快，近似优值函数的调整参数。较快的优值函数可用于迭代，并根据调整参数进行调整。

33. 发明申请

WO2006073758A2 CIRCUIT ELEMENT FUNCTION MATCHING DESPITE AUTO-GENERATED DUMMY SHAPES 审中-公开
标题翻译：电路元件功能匹配DESPITE自动生成的DUMMY形状
公开(公告)号：WO2006073758A2
公开(公告)日：2006-07-13
申请号：PCT/US2005/045787
申请日：2005-12-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , LANDIS, Howard, s.
发明人： LANDIS, Howard, s.
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Methods, systems, program products are disclosed that control placement of dummy shapes (200) about sensitive circuit elements (172) such that the dummy shapes are at least substantially similar for each circuit element even though the dummy shapes are auto-generated. In one embodiment, the invention includes providing dummy shape pattern pitch information (XP, YP) to a designer, and allowing placement of circuit elements at integer multiples of one or more of the pitches such that the dummy shapes are at least substantially similar about each instance of the circuit element. Another embodiment includes allowing placement of a marker (300) about a circuit element (372) to indicate an area in which dummy shapes (306) are to be substantially identical, and then using the marker to place the circuit element. Dummy shapes generated within the marker ensure substantially identical dummy shapes for each instance of the circuit element. The invention also includes the integrated circuits formed.
摘要翻译：公开了方法，系统，程序产品，其控制关于敏感电路元件（172）的虚拟形状（200）的放置，使得即使虚拟形状被自动生成，虚拟形状对于每个电路元件至少基本相似。在一个实施例中，本发明包括向设计者提供虚拟形状图案间距信息（XP，YP），并允许将电路元件放置在一个或多个间距的整数倍处，使得虚拟形状至少基本上相似于每个电路元件的实例。另一个实施例包括允许围绕电路元件（372）放置标记（300）以指示虚拟形状（306）基本上相同的区域，然后使用标记来放置电路元件。在标记内产生的虚拟形状确保电路元件的每个实例基本相同的虚拟形状。本发明还包括形成的集成电路。

34. 发明申请

WO2006058560A1 METHOD AND SYSTEM FOR IMPROVING THE MANUFACURABILITY OF INTEGRATED CIRCUITS 审中-公开
标题翻译：用于改善集成电路制造能力的方法和系统
公开(公告)号：WO2006058560A1
公开(公告)日：2006-06-08
申请号：PCT/EP2004/014918
申请日：2004-11-30
申请人： FREESCALE SEMICONDUCTOR, INC. , CAZEAUX, Lionel, Riviere
发明人： CAZEAUX, Lionel, Riviere
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： At a particular stage in design of an integrated circuit, DFM improvements are identified which might conflict with design requirements applicable during a subsequent stage in the design flow. These DFM improvements are "reserved" that is, they are not implemented right away. However, an instance of a DFM-optimized version of this portion of the design is generated, characterized and stored. Meta information is associated with the reserved DFM improvements, for example locations in the design which correspond to the reserved DFM improvements are tagged. If, after the subsequent stage in the design flow, processing of the metainformation (tags) shows that the reserved DFM improvement does not actually conflict with the potentially-conflicting design requirement, the corresponding reserved DFM improvement is implemented, for example, by swapping-in the stored instance of the DFM-optimized version of this portion of the design.
摘要翻译：在集成电路设计的特定阶段，识别出DFM改进可能与设计流程中后续阶段适用的设计要求相冲突。这些DFM的改进是“保留”的，即它们不是立即实现的。然而，生成，表征和存储设计的这部分的DFM优化版本的实例。元信息与保留的DFM改进相关联，例如设计中对应于保留的DFM改进的位置被标记。如果在设计流程的后续阶段，元信息（标签）的处理表明保留的DFM改进实际上并不与潜在冲突的设计要求冲突，则相应的保留的DFM改进被实现，例如，通过交换 - 在存储的DFM优化版本的这个部分设计的实例中。

35. 发明申请

WO2006024324A1 DESIGN RULE CHECKING SYSTEM 审中-公开
标题翻译：设计规则检查系统
公开(公告)号：WO2006024324A1
公开(公告)日：2006-03-09
申请号：PCT/EP2004/011076
申请日：2004-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , RIVIERE, Cazeaux, Lionel
发明人： RIVIERE, Cazeaux, Lionel
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： In a design rule checking system (10) for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a value to be assigned to systematic yield loss in cases where the geometric parameter is compliant with the design rule but takes a value close to the design rule limit.
摘要翻译：在用于检查集成电路设计是否符合规定各个几何参数的极限值的设计规则的设计规则检查系统（10）中，使用非二进制函数来建模系统产量损失随着几何参数。这使得在几何参数符合设计规则但取值接近设计规则限制的情况下，可以将值分配给系统屈服损失。

36. 发明申请

WO2006019919A2 COMPUTER-IMPLEMENTED METHODS FOR GENERATING INPUT FOR A SIMULATION PROGRAM OR GENERATING A SIMULATED IMAGE OF A RETICLE 审中-公开
标题翻译：用于生成用于模拟程序或产生模拟图像的输入的计算机实现方法
公开(公告)号：WO2006019919A2
公开(公告)日：2006-02-23
申请号：PCT/US2005/025003
申请日：2005-07-14
申请人： KLA-TENCOR TECHNOLOGIES CORP. , ZURBRICK, Larry, Steven , LEHON, Harold, William
发明人： ZURBRICK, Larry, Steven , LEHON, Harold, William
IPC分类号： G03F1/14
CPC分类号： G06F17/5009 , G03F1/72 , G06F2217/12 , Y02P90/265
摘要： Various computer-implemented methods are provided. One computer-implemented method for generating input for a simulation program includes combining information about a defect detected on a partially fabricated reticle with information about phase assigned to an area of the reticle proximate to the defect. The phase is to be added to the reticle on a level other than a level on which the defect is formed. The defect is detected on the reticle prior to addition of the phase to the reticle. Another computer-implemented method includes generating a simulated image of a defect on a reticle using information about the defect generated by inspection of one level of the reticle in combination with information about a different level on the reticle.
摘要翻译：提供了各种计算机实现的方法。用于产生用于模拟程序的输入的计算机实现的方法包括将关于在部分制作的掩模版上检测到的缺陷的信息与分配给靠近缺陷的掩模版的区域的相关信息相组合。该相位将被加到除了形成缺陷的水平以外的水平线上。在加工相位到掩模版之前，在掩模版上检测到缺陷。另一种计算机实现的方法包括使用关于通过检查一个级别的掩模版产生的缺陷的信息与掩模版上关于不同级别的信息相结合的方式生成掩模版上的缺陷的模拟图像。

37. 发明申请

WO2005008410A2 PROGRAMMABLE PROCESSOR AND METHOD WITH WIDE OPERATIONS 审中-公开
标题翻译：具有广泛操作的可编程处理器和方法
公开(公告)号：WO2005008410A2
公开(公告)日：2005-01-27
申请号：PCT/US2004022126
申请日：2004-07-12
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F20060101 , G06F12/00 , G06F17/50 , G06F
CPC分类号： G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4425 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展为大于通用寄存器或数据路径宽度的宽度来改善处理器的性能。本发明通过使用通用寄存器的内容来提供实质上大于处理器的数据路径宽度的操作数，以指定可以读取或写入多个数据路径宽度的存储器地址，以及操作数的大小和形状。另外，描述了用于实现这些指令的若干指令和装置，如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优势。

38. 发明申请

WO2003079240A2 SYSTEM AND METHOD FOR PLACEMENT OF DUMMY METAL FILLS WHILE PRESERVING DEVICE MATCHING AND/OR LIMITING CAPACITANCE INCREASE 审中-公开
标题翻译：用于在保存设备匹配和/或限制电容增加时放置金属膜的系统和方法
公开(公告)号：WO2003079240A2
公开(公告)日：2003-09-25
申请号：PCT/US2003/007497
申请日：2003-03-12
申请人： UBITECH, INC.
发明人： OH, Soo-Young
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems and methods for placement of dummy metal fills while preventing disturbance of device matching and optionally limiting capacitance increase are disclosed. A computer-automated method for locating dummy fills in an integrated circuit fabrication process generally comprises receiving as input layout of the integrated circuit and specification of device matching for the integrated circuit and locating the dummy fills in the integrated circuit according to dummy rules while preserving device matching. Locating the dummy fills may include locating the dummy fills along the at least one axis of symmetry where device matching is along an axis of symmetry and locating the dummy fills so as to preserve matching of the repeated elements where device matching is repeated matched elements. The method may also include designating at least one net of the integrated circuit as a critical net, the critical nets being only a subset of all nets of the integrated circuit, identifying metal conductors corresponding to each designated critical net from the layout file, and delineating a net blocking exclusion zone extending a distance of a minimum net blocking distance (NBD) from the metal conductor for each metal conductor identified, wherein the step of locating locates the dummy fills outside of the net blocking exclusion zone.
摘要翻译：公开了用于放置虚拟金属填充物的系统和方法，同时防止装置匹配的干扰并且可选地限制电容增加。用于在集成电路制造过程中定位虚拟填充的计算机自动化方法通常包括接收作为集成电路的输入布局和集成电路的装置匹配的规范，并且根据虚拟规则将虚拟填充定位在集成电路中，同时保留装置匹配。定位虚拟填充可以包括沿着至少一个对称轴定位虚拟填充物，其中设备匹配沿着对称轴并且定位虚拟填充，以便保留重复元件的匹配，其中设备匹配是重复的匹配元素。该方法还可以包括将集成电路的至少一个网络指定为关键网络，关键网络仅仅是集成电路的所有网络的子集，从布局文件中识别对应于每个指定的关键网络的金属导体，以及描绘网阻挡排阻区域，用于为所识别的每个金属导体延伸与金属导体的最小净阻塞距离（NBD）的距离，其中定位步骤将虚拟填充位置定位在网阻挡禁区外。

39. 发明申请

WO2019103774A1 CREATING AND EDITING GRADED MATERIAL DISTRIBUTIONS BASED ON FUNCTIONAL REQUIREMENTS 审中-公开
公开(公告)号：WO2019103774A1
公开(公告)日：2019-05-31
申请号：PCT/US2018/047026
申请日：2018-08-20
申请人： SIEMENS AKTIENGESELLSCHAFT , SIEMENS CORPORATION
发明人： MUSUVATHY, Suraj Ravi , GRUENEWALD, Thomas , DALLORO, Livio , WILLIAMS, Reed , MIRABELLA, Lucia
IPC分类号： G06F17/50 , B29C64/386 , B33Y50/02
CPC分类号： G06F17/5086 , B29C64/153 , B29C64/30 , B29C64/386 , B33Y40/00 , B33Y50/00 , B33Y50/02 , G06F17/5018 , G06F2217/08 , G06F2217/12
摘要： A method for generating graded material distributions based on functional requirements for additive manufacturing applications includes receiving a 3-D model of an object, and determining boundary conditions and target mechanical properties for the object based on user input. The object is divided into volumetric elements. A material density map for the object is generated by performing a topology optimization over the elements to assign a density measurement to each volumetric element. An interactive editing process is performed in a GUI. This process includes performing digital filtering operations on the material density map to yield an updated material density map. The process further includes using a homogenization model to effective bulk material properties of the object based on the updated material density map. A visualization of the updated material density map and the effective bulk material properties may then be presented in the GUI.

40. 发明申请

WO2019075278A1 SYSTEM AND METHOD FOR HANDLING ASSETS FOR FABRICATION 审中-公开
公开(公告)号：WO2019075278A1
公开(公告)日：2019-04-18
申请号：PCT/US2018/055523
申请日：2018-10-11
申请人： BAUDISCH, Patrick
发明人： BAUDISCH, Patrick , SILBER, Arthur
IPC分类号： G06F19/00
CPC分类号： G06F17/5086 , G06F2217/12
摘要： In one embodiment, a method generates a reusable component. The method comprises generating an export file consumable by the targeted fabrication machine, wherein all or part of the geometry represented by the export file allows translation or rotation or both to reflect a position of an asset in a 3D model containing the asset.

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