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31. 发明申请

WO2007043042A2 METHOD OF ERROR CORRECTION IN MBC FLASH MEMORY 审中-公开
标题翻译： MBC闪存中错误校正方法
公开(公告)号：WO2007043042A2
公开(公告)日：2007-04-19
申请号：PCT/IL2006/001159
申请日：2006-10-04
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD. , LITSYN, Simon , ALROD, Idan , SHARON, Eran , MURIN, Mark , LASSER, Menachem
发明人： LITSYN, Simon , ALROD, Idan , SHARON, Eran , MURIN, Mark , LASSER, Menachem
IPC分类号： G06F19/00
CPC分类号： G06F11/1072
摘要： A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.
摘要翻译：多个逻辑页面与对应的ECC位一起存储在MBC闪速存储器中，其中至少一个MBC单元存储来自多于一个的逻辑页面的位，以及至少一个ECC位应用于两个或多个逻辑页面。当从存储器读取页面时，读取的数据位使用读取的ECC位进行校正。或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。当读取联合码字时，从读取的码字中恢复逻辑比特。本发明的范围还包括对应的存储器件，这种存储器件的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

32. 发明申请

WO2013032892A1 SYSTEM AND METHOD OF COPYING DATA 审中-公开
标题翻译：复制数据的系统和方法
公开(公告)号：WO2013032892A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/052231
申请日：2012-08-24
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G11C29/52
摘要： A method of copying data includes receiving a command instructing copying of data from a source location in the memory die to a destination location in the memory die. The method includes determining if a criterion is met, including comparing a predefined parameter to a dynamic threshold. In response to determining that the criterion is met, the method includes executing the copying by moving the data from the source location in the memory die to the controller die and, after moving the data to the controller die, moving an error-corrected version of the data from the controller die to the destination location in the memory die. In response to determining that the criterion is not met, the method includes executing the copying by moving the data inside the memory die source location to the destination location without moving the data to the controller die.
摘要翻译：复制数据的方法包括：接收指令从存储器管芯中的源位置复制数据到存储管芯中的目标位置的命令。该方法包括确定是否满足标准，包括将预定义参数与动态阈值进行比较。响应于确定满足标准，该方法包括通过将数据从存储器管芯中的源位置移动到控制器管芯来执行复制，并且在将数据移动到控制器管芯之后，移动错误校正版本来自控制器的数据死亡到存储器管芯中的目的位置。响应于确定不符合标准，该方法包括通过将存储器管芯源位置内的数据移动到目标位置来执行复制，而不将数据移动到控制器管芯。

33. 发明申请

WO2013018080A1 ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS 审中-公开
标题翻译：具有减少内存和电源要求的错误修正解码
公开(公告)号：WO2013018080A1
公开(公告)日：2013-02-07
申请号：PCT/IL2011/000617
申请日：2011-07-31
申请人： SANDISK TECHNOLOGIES, INC., A TEXAS CORPORATION , SHARON, Eran , ALROD, Idan , FAINZILBER, Omer , LITSYN, Simon
发明人： SHARON, Eran , ALROD, Idan , FAINZILBER, Omer , LITSYN, Simon
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , H03M13/1117 , H03M13/3715 , H03M13/6502
摘要： An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.
摘要翻译：提供了一种示例性方法，其包括接收包括多个比特的码字的表示，并且将比特与表示比特的相应多个一比特硬比特值和表示多个比特的度量的多比特软比特值相关联各个硬比特值的可靠性。该方法包括用于多个迭代中的每一个，作为该子集的比特的当前硬比特值的函数来更新比特的相应子集的一个或多个比特的硬比特/软比特值，以及当前相应位的硬比特和软比特值。对于两次迭代，其中对于两次迭代的子集的每个位的当前硬比特和软比特值是相同的，则在两次迭代之一期间为子集的任何比特更新的硬比特/软比特值与在两次迭代中的另一个中相应位计算的相同。

34. 发明申请

WO2011128867A1 MULTIPLE PROGRAMMING OF FLASH MEMORY WITHOUT ERASE 审中-公开
标题翻译：无擦除的闪存存储器的多个编程
公开(公告)号：WO2011128867A1
公开(公告)日：2011-10-20
申请号：PCT/IB2011/051613
申请日：2011-04-14
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , ALROD, Idan , LITSYN, Simon , ILANI, Ishai
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon , ILANI, Ishai
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/102 , G06F12/02 , G11C11/5628 , G11C16/349
摘要： To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.
摘要翻译：为了顺次地在多个存储单元中存储数量相等的第一和第二多个输入位，第一变换将第一输入位变换为第一多个变换位。单元的第一部分被编程为根据位序列到单元级别的映射来存储第一变换的位，但是如果第一变换具有可变的输出长度，则只有当足够少的第一变换位适合于第一细胞部分。然后，在不擦除包括第一部分的第二单元部分的情况下，如果根据映射通过第二输入位的第二变换获得的表示第二多个变换位的第二部分的单元的各个级别是从当前单元级可访问，第二部分被编程为存储第二转换位。

35. 发明申请

WO2010092536A1 APPARATUS AND METHOD FOR ENHANCING FLASH ENDURANCE BY ENCODING DATA 审中-公开
标题翻译：通过编码数据提高闪存耐久性的装置和方法
公开(公告)号：WO2010092536A1
公开(公告)日：2010-08-19
申请号：PCT/IB2010/050621
申请日：2010-02-11
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , LITSYN, Simon , ALROD, Idan
发明人： SHARON, Eran , LITSYN, Simon , ALROD, Idan
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G06F12/0246 , G11C7/1006 , G11C11/5628 , G11C16/349 , G11C16/3495 , G11C2211/5647
摘要： Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance.
摘要翻译：通过使用相对于位模式对单元状态的映射具有向下渐近偏移的整形编码并根据该映射来编程一些单元，将输入位存储在存储器单元中，将输入位映射到更大数目的变换位中的位模式到单元状态。在被编程为存储任何其他位之前，编程的单元被擦除。本发明牺牲记忆能力以增加耐力。

36. 发明申请

WO2010035241A1 METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES 审中-公开
标题翻译：闪存中自适应编码的方法和系统
公开(公告)号：WO2010035241A1
公开(公告)日：2010-04-01
申请号：PCT/IB2009/054222
申请日：2009-09-27
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, menahem
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, menahem
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3404 , G06F11/1072 , G11C7/1006 , G11C11/5628 , G11C29/00 , G11C2211/5641
摘要： Bits are stored by attempting to set parameter value(s) of (a) cell(s) to represent some of the bits. In accordance with the attempt, an adaptive mapping of the bits to value ranges is provided and the value(s) is/are adjusted accordingly as needed. Or, to store (a) bit(s) in (a) cell(s), a default mapping of the bit(s) to a predetermined set of value ranges is provided and an attempt is made to set the cell value(s) accordingly. If, for one of the cells, the attempt sets the value such that the desired range is inaccessible, an adaptive mapping is provided such that the desired range is accessible. Or, to store (a) bit(s) in (a) cell(s), several mappings of the bϊt(s) to a predetermined set of ranges is provided. Responsive to an attempt to set the cell value(s) according to one of the mappings, the mapping to actually use is selected.
摘要翻译：通过尝试设置（a）单元的参数值来表示某些位来存储位。根据该尝试，提供了比特到值范围的自适应映射，并且根据需要相应地调整该值。或者，为了将（a）位（a）存储在（a）单元中，提供了该位的默认映射到预定的一组值范围，并尝试设置单元值（s ）。如果对于其中一个小区，尝试将值设置为使得期望的范围不可访问，则提供自适应映射，使得期望的范围是可访问的。或者，为了将（a）位（a）存储在（a）单元中，提供了b≤t（s）的几个映射到预定的范围集合。响应于根据映射之一设置单元格值，选择实际使用的映射。

37. 发明申请

WO2008075337A1 LAZY SCHEDULING FOR LDPC DECODING 审中-公开
标题翻译：用于LDPC解码的LAZY调度
公开(公告)号：WO2008075337A1
公开(公告)日：2008-06-26
申请号：PCT/IL2007/001528
申请日：2007-12-11
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , LITSYN, Simon
发明人： SHARON, Eran , LITSYN, Simon
IPC分类号： H03M13/11
CPC分类号： H03M13/1137 , H03M13/1131 , H03M13/114
摘要： A decoder, of a codeword representation that includes a plurality of soft bits, includes a plurality of functional modules for updating the soft bits iteratively. Whether each soft bit participates in at least some iterations is determined according to a selection criterion, e.g., probabilistically, or according to iteration number, or according to the soft bit's iteration history. For example, each soft bit might participate in some or all iterations with a probability that is a function of both the iteration number and a reliability measure of that soft bit. Preferably, the functional modules are LDPC functional modules that address variable nodes sequentially for exchanging messages with corresponding check nodes. The decoder may be implemented in circuitry of a memory, in a controller of a memory device, or in a host of a memory device.
摘要翻译：包括多个软比特的码字表示的解码器包括用于迭代地更新软比特的多个功能模块。每个软比特是否参与至少一些迭代，根据选择标准，例如概率地，或根据迭代次数，或根据软比特迭代历史来确定。例如，每个软比特可能参与一些或所有迭代，其概率是该软比特的迭代次数和可靠性度量的函数。优选地，功能模块是LDPC功能模块，其顺序地寻址可变节点以与相应的校验节点交换消息。解码器可以在存储器的电路，存储器件的控制器或存储器件的主机中实现。

38. 发明申请

WO2007046084A3 PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY 审中-公开
公开(公告)号：WO2007046084A3
公开(公告)日：2007-04-26
申请号：PCT/IL2006/001175
申请日：2006-10-15
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD. , LITSYN, Simon , ALROD, Idan , SHARON, Eran , MURIN, Mark , LASSER, Menachem
发明人： LITSYN, Simon , ALROD, Idan , SHARON, Eran , MURIN, Mark , LASSER, Menachem
IPC分类号： G11C29/00 , H03M13/00
摘要： Data that are stored in cells of a multi-bit-per cell memory (42) according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non- systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

39. 发明申请

WO2005086445A2 DUAL CARRIER MODULATOR FOR A MULTIBAND OFDM TRANSCEIVER 审中-公开
标题翻译：用于多载波OFDM收发器的双载波调制器
公开(公告)号：WO2005086445A2
公开(公告)日：2005-09-15
申请号：PCT/EP2005/002259
申请日：2005-03-03
申请人： INFINEON TECHNOLOGIES AG , ERLICH, Yossi , LITSYN, Simon , SHARON, Eran
发明人： ERLICH, Yossi , LITSYN, Simon , SHARON, Eran
IPC分类号： H04L27/26
CPC分类号： H04L27/2608 , H04B1/7176 , H04L27/3405
摘要： Dual Carrier Modulator (DCM) for a Multiband OFDM (Orthogonal Frequency Division Multiplexing) Transceiver of a Ultra Wide Band (UWB) wireless personal access network transmitting OFDM modulated symbols, wherein each OFDM symbol is modulated by a predetermined number (N CBPS ) of encoded bits, said Dual Carrier Modulator (1) comprising: (g) a grouping unit (1-1) for grouping N CBPS encoded bits of a serial bit stream into bit groups each having a predetermined number (m) of bits; (h) a mapping unit (1-2) for mapping each bit group received from said grouping unit to complex symbols(y) using an orthogonal transform; and (i) a reordering unit (1-3) for reordering the complex symbols (y) mapped by said mapping unit, wherein each complex symbol (y) is provided to modulate a corresponding data tone of an OFDM symbol.
摘要翻译：用于发射OFDM调制符号的超宽带（UWB）无线个人接入网络的多频带OFDM（正交频分复用）收发器的双载波调制器（DCM），其中每个OFDM符号被编码的预定数量（N CBPS）调制所述双载波调制器（1）包括：（g）用于将串行比特流的NCBPS编码比特分组成每个具有预定数量（m）比特的比特组的分组单元（1-1）（h）用于使用正交变换将从所述分组单元接收的每个位组映射到复数符号（y）的映射单元（1-2）以及（i）用于对由所述映射单元映射的复符号（y）进行重新排序的重排序单元（1-3），其中提供每个复数符号（y）以调制OFDM符号的相应数据音调。

40. 发明申请

WO2014007941A1 METHOD AND SYSTEM FOR EXTENDING THE EFFECTIVE VOLTAGE WINDOW OF A MEMORY CELL 审中-公开
标题翻译：用于扩展存储单元的有效电压窗口的方法和系统
公开(公告)号：WO2014007941A1
公开(公告)日：2014-01-09
申请号：PCT/US2013/044848
申请日：2013-06-07
申请人： SANDISK TECHNOLOGIES, INC. , SHARON, Eran
发明人： SHARON, Eran
IPC分类号： G11C11/56
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642
摘要： Methods for operating a non-volatile storage system in which cross-coupling effects are utilized to extend the effective threshold voltage window of a memory cell and to embed additional information within the extended threshold voltage window are described. In some cases, additional information may be embedded within a memory cell storing the highest programming state if the memory cell is in a high boosting environment by splitting the highest programming state into two substates and programming the memory cell to one of the two substates based on the additional information. A memory cell may be in a high boosting environment if its neighboring memory cells are in a high programmed state. Additional information may also be embedded within a memory cell storing the lowest programming state if the memory cell is in a low boosting environment. The additional information may include error correction information.
摘要翻译：描述用于操作非易失性存储系统的方法，其中利用交叉耦合效应来扩展存储器单元的有效阈值电压窗口并且在扩展阈值电压窗口内嵌入附加信息。在某些情况下，如果通过将最高编程状态分为两个子状态，存储单元处于高增益环境中，则附加信息可嵌入存储最高编程状态的存储单元中，并且基于附加信息。如果存储器单元的相邻存储器单元处于高编程状态，则其可以处于高增益环境中。如果存储器单元处于低增压环境中，附加信息也可以被嵌入在存储最低编程状态的存储单元中。附加信息可以包括纠错信息。

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