专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007046084A3 PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY 审中-公开
公开(公告)号：WO2007046084A3
公开(公告)日：2007-04-26
申请号：PCT/IL2006/001175
申请日：2006-10-15
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD. , LITSYN, Simon , ALROD, Idan , SHARON, Eran , MURIN, Mark , LASSER, Menachem
发明人： LITSYN, Simon , ALROD, Idan , SHARON, Eran , MURIN, Mark , LASSER, Menachem
IPC分类号： G11C29/00 , H03M13/00
摘要： Data that are stored in cells of a multi-bit-per cell memory (42) according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non- systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

2. 发明申请

WO2007043042A2 METHOD OF ERROR CORRECTION IN MBC FLASH MEMORY 审中-公开
标题翻译： MBC闪存中错误校正方法
公开(公告)号：WO2007043042A2
公开(公告)日：2007-04-19
申请号：PCT/IL2006/001159
申请日：2006-10-04
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD. , LITSYN, Simon , ALROD, Idan , SHARON, Eran , MURIN, Mark , LASSER, Menachem
发明人： LITSYN, Simon , ALROD, Idan , SHARON, Eran , MURIN, Mark , LASSER, Menachem
IPC分类号： G06F19/00
CPC分类号： G06F11/1072
摘要： A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.
摘要翻译：多个逻辑页面与对应的ECC位一起存储在MBC闪速存储器中，其中至少一个MBC单元存储来自多于一个的逻辑页面的位，以及至少一个ECC位应用于两个或多个逻辑页面。当从存储器读取页面时，读取的数据位使用读取的ECC位进行校正。或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。当读取联合码字时，从读取的码字中恢复逻辑比特。本发明的范围还包括对应的存储器件，这种存储器件的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

3. 发明申请

WO2007057885A2 METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION 审中-公开
标题翻译：用于多相位错误校正的方法和装置
公开(公告)号：WO2007057885A2
公开(公告)日：2007-05-24
申请号：PCT/IL2006/001305
申请日：2006-11-13
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menachem
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menachem
IPC分类号： H04K1/02
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3715 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。如果解码失败之一，则解码失败的剩余子集至少部分地根据所选子集进行解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

4. 发明申请

WO2011128867A1 MULTIPLE PROGRAMMING OF FLASH MEMORY WITHOUT ERASE 审中-公开
标题翻译：无擦除的闪存存储器的多个编程
公开(公告)号：WO2011128867A1
公开(公告)日：2011-10-20
申请号：PCT/IB2011/051613
申请日：2011-04-14
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , ALROD, Idan , LITSYN, Simon , ILANI, Ishai
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon , ILANI, Ishai
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/102 , G06F12/02 , G11C11/5628 , G11C16/349
摘要： To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.
摘要翻译：为了顺次地在多个存储单元中存储数量相等的第一和第二多个输入位，第一变换将第一输入位变换为第一多个变换位。单元的第一部分被编程为根据位序列到单元级别的映射来存储第一变换的位，但是如果第一变换具有可变的输出长度，则只有当足够少的第一变换位适合于第一细胞部分。然后，在不擦除包括第一部分的第二单元部分的情况下，如果根据映射通过第二输入位的第二变换获得的表示第二多个变换位的第二部分的单元的各个级别是从当前单元级可访问，第二部分被编程为存储第二转换位。

5. 发明申请

WO2010092536A1 APPARATUS AND METHOD FOR ENHANCING FLASH ENDURANCE BY ENCODING DATA 审中-公开
标题翻译：通过编码数据提高闪存耐久性的装置和方法
公开(公告)号：WO2010092536A1
公开(公告)日：2010-08-19
申请号：PCT/IB2010/050621
申请日：2010-02-11
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , LITSYN, Simon , ALROD, Idan
发明人： SHARON, Eran , LITSYN, Simon , ALROD, Idan
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G06F12/0246 , G11C7/1006 , G11C11/5628 , G11C16/349 , G11C16/3495 , G11C2211/5647
摘要： Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance.
摘要翻译：通过使用相对于位模式对单元状态的映射具有向下渐近偏移的整形编码并根据该映射来编程一些单元，将输入位存储在存储器单元中，将输入位映射到更大数目的变换位中的位模式到单元状态。在被编程为存储任何其他位之前，编程的单元被擦除。本发明牺牲记忆能力以增加耐力。

6. 发明申请

WO2010035241A1 METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES 审中-公开
标题翻译：闪存中自适应编码的方法和系统
公开(公告)号：WO2010035241A1
公开(公告)日：2010-04-01
申请号：PCT/IB2009/054222
申请日：2009-09-27
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, menahem
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, menahem
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3404 , G06F11/1072 , G11C7/1006 , G11C11/5628 , G11C29/00 , G11C2211/5641
摘要： Bits are stored by attempting to set parameter value(s) of (a) cell(s) to represent some of the bits. In accordance with the attempt, an adaptive mapping of the bits to value ranges is provided and the value(s) is/are adjusted accordingly as needed. Or, to store (a) bit(s) in (a) cell(s), a default mapping of the bit(s) to a predetermined set of value ranges is provided and an attempt is made to set the cell value(s) accordingly. If, for one of the cells, the attempt sets the value such that the desired range is inaccessible, an adaptive mapping is provided such that the desired range is accessible. Or, to store (a) bit(s) in (a) cell(s), several mappings of the bϊt(s) to a predetermined set of ranges is provided. Responsive to an attempt to set the cell value(s) according to one of the mappings, the mapping to actually use is selected.
摘要翻译：通过尝试设置（a）单元的参数值来表示某些位来存储位。根据该尝试，提供了比特到值范围的自适应映射，并且根据需要相应地调整该值。或者，为了将（a）位（a）存储在（a）单元中，提供了该位的默认映射到预定的一组值范围，并尝试设置单元值（s ）。如果对于其中一个小区，尝试将值设置为使得期望的范围不可访问，则提供自适应映射，使得期望的范围是可访问的。或者，为了将（a）位（a）存储在（a）单元中，提供了b≤t（s）的几个映射到预定的范围集合。响应于根据映射之一设置单元格值，选择实际使用的映射。

7. 发明申请

WO2011010286A4 COMPACT DECODING OF PUNCTURED CODES 审中-公开
公开(公告)号：WO2011010286A4
公开(公告)日：2011-01-27
申请号：PCT/IB2010/053317
申请日：2010-07-21
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , ALROD, Idan , LITSYN, Simon
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon
IPC分类号： H03M13/00 , H03M13/25 , H04L1/00
摘要： k input bits are encoded according to a code with which is associated a m x n=m+k parity check matrix H . The resulting codeword is punctured, with n' bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H' that is smaller than H . For example, H' is m'=m~(n-n ') x n' and is derived by merging selected rows of H . Alternatively, H has at most m rows and fewer than n columns but more than n' columns. Alternatively, H has fewer than m'=m-(n-n') rows and fewer than n' columns.

8. 发明申请

WO2009156935A4 USING DAMPING FACTORS TO OVERCOME LDPC TRAPPING SETS 审中-公开
公开(公告)号：WO2009156935A4
公开(公告)日：2009-12-30
申请号：PCT/IB2009/052662
申请日：2009-06-22
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , LITSYN, Simon , ALROD, Idan
发明人： SHARON, Eran , LITSYN, Simon , ALROD, Idan
IPC分类号： H03M13/11
摘要： To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between JV bit nodes and N-K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules.

9. 发明申请

WO2009104063A1 METHOD AND DEVICE FOR ADAPTIVE DECODING USING GLOBAL PARITY BITS 审中-公开
标题翻译：使用全球特征位自适应解码的方法和装置
公开(公告)号：WO2009104063A1
公开(公告)日：2009-08-27
申请号：PCT/IB2008/055477
申请日：2008-12-21
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menahem
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menahem
IPC分类号： H03M13/29 , G06F11/10 , H03M13/11
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3707 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many- to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. A subset whose decoding is terminated is decoded again, at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。解码终止的子集至少部分地根据所选择的子集被再次解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

10. 发明申请

WO2008129533A1 ADAPTIVE DYNAMIC READING OF FLASH MEMORIES 审中-公开
标题翻译：闪存的自适应动态读取
公开(公告)号：WO2008129533A1
公开(公告)日：2008-10-30
申请号：PCT/IL2008/000506
申请日：2008-04-13
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , LITSYN, Simon , ALROD, Idan , SHARON, Eran
发明人： LITSYN, Simon , ALROD, Idan , SHARON, Eran
IPC分类号： G11C16/28 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： Each of a plurality of flash memory cells is programmed to a respective one of L ≥2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m ≥2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells.
摘要翻译：多个闪存单元中的每一个被编程为阈值电压窗口内的L = 2个阈值电压状态中的相应一个。根据阈值电压窗口内的一些或所有单元的阈值电压与两个或更多个m = 2个阈值电压间隔的比较，调整阈值电压函数的参数值。基于这些值来选择用于读取单元的参考电压。或者，m阈值电压间隔跨越阈值电压窗口，并且基于阈值电压处于间隔中的单元的数量而将各个阈值电压状态分配给单元，而不重新读取单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式