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31. 发明申请

WO2007148159A1 A METHOD AND DEVICE FOR POWER MANAGEMENT 审中-公开
标题翻译：一种用于电力管理的方法和装置
公开(公告)号：WO2007148159A1
公开(公告)日：2007-12-27
申请号：PCT/IB2006/052033
申请日：2006-06-22
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid
发明人： ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device and method for power management. The method includes receiving an indication about a load of a circuit (610), determining (620) at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining (630) at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing (640) at least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter.
摘要翻译：一种用于电源管理的设备和方法。该方法包括接收关于电路的负载的指示（610），在至少一个长周期期间考虑到电路负载模式来确定（620）至少一个长期激活参数; 响应于所述电路的预期短周期负载变化来确定（630）至少一个短期激活参数; 以及响应于所述长期激活参数并响应于所述短期供应参数而提供（640）至少一个时钟信号和至少一个电源电压。

32. 发明申请

WO2006120507A1 METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES 审中-公开
标题翻译：降低功率的方法和具有降低功率的装置
公开(公告)号：WO2006120507A1
公开(公告)日：2006-11-16
申请号：PCT/IB2005/051539
申请日：2005-05-11
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
IPC分类号： G06F1/32
CPC分类号： G06F1/3225 , G06F1/3275 , G06F1/3287 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method (100) for power reduction, the method includes determining (140) whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively (150) providing power to at least a portion of a component of an integrated circuit during a low power mode. A device (10) having power reduction capabilities, the device includes power switching circuitry (30) adapted to selectively provide power to at least a portion (22, 24, 26, 28) of a component (20) of the device during a low power mode, and a power management circuitry (40) adapted to determine whether to power down at least the portion (22, 24, 26, 28) of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion (22, 24, 26, 28) of the component (20) during the low power.
摘要翻译：一种用于功率降低的方法（100），所述方法包括确定（140）响应于所估计的功率增益与由所述至少部分断电而产生的估计功率损耗之间的关系来确定（140）所述部件的至少部分的掉电在低功率模式期间选择性地（150）向集成电路的部件的至少一部分提供电力。一种具有功率降低能力的设备（10），该设备包括功率切换电路（30），其适于在低电平期间选择性地向设备的部件（20）的一部分（22,24,26,28）提供功率功率模式和功率管理电路（40），其适于在低功率模式期间响应于估计的功率增益和功率模式之间的关系来确定是否在低功率模式期间对组件的至少部分（22,24,26,28）在低功率期间由部件（20）的至少部分（22,24,26,28）断电导致的估计的功率损耗。

33. 发明申请

WO2013079995A1 METHOD FOR PLACING OPERATIONAL CELLS IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中放置操作电池的方法
公开(公告)号：WO2013079995A1
公开(公告)日：2013-06-06
申请号：PCT/IB2011/055417
申请日：2011-12-01
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , BERKOVITZ, Asher , PRIEL, Michael
发明人： ROZEN, Anton , BERKOVITZ, Asher , PRIEL, Michael
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/78 , G06F2217/84 , Y02E60/76 , Y04S40/22
摘要： There is provided a method of placing a plurality of operational cells of a semiconductor device within a semiconductor layout, comprising determining timing data for each of the plurality of operational cells, determining switching activity from RTL or design constraints for each of the plurality of operational cells, determining power grid switch locations relative to each of the plurality of operational cells, deriving a cost function based upon the determined timing data, determined switching activity from RTL/design constraints and determined relative power grid switch locations and initially placing the plurality of operational cells according to the derived cost function.
摘要翻译：提供了一种将半导体器件的多个操作单元放置在半导体布局内的方法，包括确定多个操作单元中的每一个的定时数据，从RTL确定切换活动或为多个操作单元中的每一个设计约束确定相对于所述多个操作小区中的每一个的电网交换位置，基于所确定的定时数据导出成本函数，根据来自RTL /设计约束和所确定的相对电网交换机位置确定的交换活动，并且首先将所述多个操作单元根据衍生成本函数。

34. 发明申请

WO2011117671A1 POWER GATING CONTROL MODULE, INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM, ELECTRONIC DEVICE, AND METHOD THEREFOR 审中-公开
标题翻译：功率增益控制模块，集成电路设备，信号处理系统，电子设备及其方法
公开(公告)号：WO2011117671A1
公开(公告)日：2011-09-29
申请号：PCT/IB2010/051231
申请日：2010-03-22
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , ROZEN, Anton , SHOSHANY, Yossi
发明人： PRIEL, Michael , ROZEN, Anton , SHOSHANY, Yossi
IPC分类号： H04B1/16
CPC分类号： H03K19/0016 , G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： An integrated circuit device (205) comprising at least one signal processing module (210) and a power gating control module (220) arranged to control gating of at least one power supply to at least a part of the at least one signal processing module (210). The power gating control module (220) is arranged to receive at least one operating parameter (230); configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter (230); and apply power gating for at least part of the at least one signal processing module (210) in accordance with the at least one configured power gating setting.
摘要翻译：一种集成电路装置（205），包括至少一个信号处理模块（210）和电源门控控制模块（220），其被布置成控制至少一个电源的至少一个电源的门控，所述至少一个电源至少部分至少一个信号处理模块 210）。电源门控控制模块（220）被布置成接收至少一个操作参数（230）; 至少部分地基于所述至少一个接收的操作参数（230）来配置所述电力门控控制模块的至少一个电力门控设置; 并且根据所述至少一个配置的电源门控设置为所述至少一个信号处理模块（210）的至少一部分施加电力门控。

35. 发明申请

WO2009115864A1 A METHOD FOR PROTECTING A CRYPTOGRAPHIC MODULE AND A DEVICE HAVING CRYPTOGRAPHIC MODULE PROTECTION CAPABILITIES 审中-公开
标题翻译：用于保护晶片模块的方法和具有编码模块保护能力的装置
公开(公告)号：WO2009115864A1
公开(公告)日：2009-09-24
申请号：PCT/IB2008/051038
申请日：2008-03-19
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , ASHKENAZI, Asaf , KUZMIN, Dan , ROZEN, Anton
发明人： PRIEL, Michael , ASHKENAZI, Asaf , KUZMIN, Dan , ROZEN, Anton
IPC分类号： G06F21/00
CPC分类号： G06F21/558 , G06F21/554 , G06F21/755 , G06F21/86
摘要： A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions.
摘要翻译：一种用于保护密码模块的设备和方法，该方法包括：当物理参数具有与加密模块正常工作的标称参数值不同的第一值时，估计适于故障的电路的功能。当物理参数具有与标称参数值不同的第二值并且第一值和标称参数值之间的差小于第二值和标称参数值之间的差时，加密模块发生故障。如果估计电路发生故障，则应用加密模块保护措施。

36. 发明申请

WO2008129362A2 DEVICE AND METHOD FOR STATE RETENTION POWER GATING 审中-公开
标题翻译：用于状态保持功率增益的装置和方法
公开(公告)号：WO2008129362A2
公开(公告)日：2008-10-30
申请号：PCT/IB2007/051444
申请日：2007-04-20
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton
CPC分类号： H03K19/0016 , G01R31/318533 , H03K17/24 , H03K21/403
摘要： A device (100) for state retention power gating, the device (100) includes a group of circuits (110 (1) - 110 (4) ) , each circuit is characterized by a reset state, wherein the device (100) is characterized by including: a first memory entity (130, 530 (1) , 530 (8) ) adapted to save during a shut down period of the group circuits (110 (1) - 110 (4) ) , at least one location of at least one non-reset- state circuit of the group of circuits.
摘要翻译：一种用于状态保持电源门控的设备（100），所述设备（100）包括一组电路（110（1）至110（4）），每个电路的特征在于复位状态，其中所述设备（100）通过包括：第一存储器实体（130,530（1），530（8）），适于在组电路（110（1）至110（4））的关闭时段期间保存，至少一个位置该组电路中至少有一个非复位状态电路。

37. 发明申请

WO2008015495A1 DEVICE AND METHOD FOR POWER MANAGEMENT 审中-公开
标题翻译：用于电源管理的设备和方法
公开(公告)号：WO2008015495A1
公开(公告)日：2008-02-07
申请号：PCT/IB2006/052671
申请日：2006-08-03
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton
IPC分类号： G06F1/32
CPC分类号： G06F1/08 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device having power management capabilities and a method (300) for power management, the method (300) includes: providing (310) a clock signal and a supply voltage to at least one component of a device; detecting (330) a timing error; delaying (350) by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining (370) a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.
摘要翻译：一种具有电源管理功能的设备和用于电源管理的方法（300），所述方法（300）包括：向设备的至少一个组件提供（310）时钟信号和电源电压; 检测（330）定时误差; 响应于检测到的定时误差延迟（350）一小时的时钟周期，提供给至少一个组件的时钟信号; 以及响应于至少一个检测到的定时误差来确定（370）时钟信号频率和电源电压的电平。

38. 发明申请

WO2007049100A1 SYSTEM AND METHOD FOR CONTROLLING VOLTAGE LEVEL AND CLOCK FREQUENCY SUPPLIED TO A SYSTEM 审中-公开
标题翻译：用于控制提供给系统的电压电平和时钟频率的系统和方法
公开(公告)号：WO2007049100A1
公开(公告)日：2007-05-03
申请号：PCT/IB2005/053518
申请日：2005-10-27
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , GUBESKYS, Arik , PRIEL, Michael
发明人： ROZEN, Anton , GUBESKYS, Arik , PRIEL, Michael
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system (100) that includes at least one component (100) adapted to execute at least one application, characterized by including a controller (401) adapted to receive at least one load indication of at least one component of the system and to selectively alter at least one control parameter of a voltage and clock frequency management scheme; whereas the system (100) is adapted to apply the voltage and clock frequency management scheme. A method (600) for controlling voltage level and clock frequency supplied to a system, the method includes receiving (620) at least one load indication of at least one component of the system; characterized repeating the stages of: selectively altering (650) at least one control parameter of a voltage and clock frequency management scheme; and applying (660) the voltage and clock frequency management scheme.
摘要翻译：一种包括适于执行至少一个应用的至少一个组件（100）的系统（100），其特征在于包括适于接收系统的至少一个组件的至少一个负载指示的控制器（401），并且选择性地改变电压和时钟频率管理方案的至少一个控制参数; 而系统（100）适于施加电压和时钟频率管理方案。一种用于控制提供给系统的电压电平和时钟频率的方法（600），所述方法包括接收（620）所述系统的至少一个组件的至少一个负载指示; 其特征在于重复以下阶段：选择性地（650）电压和时钟频率管理方案的至少一个控制参数; 并应用（660）电压和时钟频率管理方案。

39. 发明申请

WO2006100533A1 METHOD FOR RACE PREVENTION AND A DEVICE HAVING RACE PREVENTION CAPABILITIES 审中-公开
标题翻译：预防方法和具有预防能力的装置
公开(公告)号：WO2006100533A1
公开(公告)日：2006-09-28
申请号：PCT/IB2005/000756
申请日：2005-03-23
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton
IPC分类号： H03K3/3562 , G01R31/3185
CPC分类号： G01R31/318541 , G01R31/318536 , H03K3/0375
摘要： A method (400) for race prevention and a device (100) that has race prevention capabilities. The method (400) includes: selectively providing (410) data or scan data to a input latching logic, activating (420) the input latching logic for a first scan mode activation period, introducing (430) a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating (440) a output latching logic, connected to the input latching logic for a second scan mode activation period. The device (100) includes: an interface logic (110), a input latching logic (120), a output latching logic (130) and a control logic (150). The interface logic (110) is adapted to selectively provide data or scan data to the input latching logic (120). The control logic (150) is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic (120) and between a start point of a second scan mode activation period of the output latching logic (130).
摘要翻译：一种用于防止种族的方法（400）和具有防止竞争能力的装置（100）。方法（400）包括：选择性地将（410）数据或扫描数据提供给输入锁存逻辑，激活（420）输入锁存逻辑用于第一扫描模式激活周期，引入（430）在第一扫描模式激活周期和第二扫描模式激活周期，以及激活（440）输出锁存逻辑，连接到所述输入锁存逻辑用于第二扫描模式激活周期。设备（100）包括：接口逻辑（110），输入锁存逻辑（120），输出锁存逻辑（130）和控制逻辑（150）。接口逻辑（110）适于选择性地向输入锁存逻辑（120）提供数据或扫描数据。控制逻辑（150）适于在输入锁存逻辑（120）的第一扫描模式激活周期的终点与输出锁存逻辑（120）的第二扫描模式激活周期的起始点之间引入实质的时间差（130）。

40. 发明申请

WO2014080244A1 PROCESSOR CORE ARRANGEMENT, COMPUTING SYSTEM AND METHODS FOR DESIGNING AND OPERATING A PROCESSOR CORE ARRANGEMENT 审中-公开
标题翻译：处理器核心安排，计算系统和设计和操作处理器核心安排的方法
公开(公告)号：WO2014080244A1
公开(公告)日：2014-05-30
申请号：PCT/IB2012/056630
申请日：2012-11-22
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid , SOFER, Sergey
发明人： ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid , SOFER, Sergey
IPC分类号： G06F9/46 , G06F9/455
CPC分类号： G06F9/30189 , G06F1/324 , G06F9/28 , G06F9/48 , G06F17/5045 , G06F2217/68 , G06F2217/78 , Y02D10/126
摘要： The invention relates to a method of designing a processor core arrangement (10) which comprises a first processor core (12) for operation at a first operation frequency and having an associated first leakage and a second processor core (12) for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the first leakage. The processor core arrangement (10) is capable of switching from the first processor core (12) to the second processor core (14) and vice versa. The method comprises: simulating said processor core arrangement to determine a reference leakage of said first processor core and said second processor core, said first processor core having an SRPG feature in said simulation; and setting said second operation frequency such that the sum of said first leakage and said second leakage is substantially equal to said reference leakage. The method further comprises providing said first processor core (12) and said second processor core (14) but not providing said SRPG feature.
摘要翻译：本发明涉及一种设计处理器核心布置（10）的方法，该处理器核心布置（10）包括用于以第一操作频率操作并具有相关联的第一泄漏的第一处理器核心（12）和用于在第二操作频率下操作的第二处理器核心操作频率低于第一操作频率，并且具有低于第一泄漏的相关联的第二泄漏。处理器核心布置（10）能够从第一处理器核心（12）切换到第二处理器核心（14），反之亦然。该方法包括：模拟所述处理器核心布置以确定所述第一处理器核心和所述第二处理器核心的参考泄漏，所述第一处理器核心在所述模拟中具有SRPG特征; 以及设定所述第二操作频率，使得所述第一泄漏和所述第二泄漏的总和基本上等于所述参考泄漏。该方法还包括提供所述第一处理器核心（12）和所述第二处理器核心（14），但不提供所述SRPG特征。

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