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21. 发明申请

WO2019169078A1 FLASH MEMORY DEVICE WITH DATA FRAGMENT FUNCTION 审中-公开
公开(公告)号：WO2019169078A1
公开(公告)日：2019-09-06
申请号：PCT/US2019/019959
申请日：2019-02-28
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , VUONG, Hung
IPC分类号： G11C16/06 , G06F12/06 , G06F12/0846 , G06F13/16 , G11C16/32 , G06F3/06 , G06F12/02
摘要： Methods and apparatuses to fragment data in a flash memory device are presented. The apparatus includes a host configured to request a flash memory device, via a memory bus, to fragment data stored in the flash memory device in response to a determination of a data fragmentation status of the flash memory device exceeding a threshold. The method includes determining a data fragmentation status of the flash memory device exceeding a threshold and requesting, by a host, the flash memory device to fragment data stored in the flash memory device in response to the determining the data fragmentation status exceeding the threshold.

22. 发明申请

WO2018057244A1 DYNAMIC CACHE PARTITIONING THROUGH HILL-CLIMBING 审中-公开
标题翻译：通过爬山进行动态高速缓存分区
公开(公告)号：WO2018057244A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/048850
申请日：2017-08-28
申请人： QUALCOMM INCORPORATED
发明人： AL SHEIKH, Rami, Mohammad, A. , CAIN, Harold, Wade, III
IPC分类号： G06F12/0811 , G06F12/084 , G06F12/123 , G06F12/0864 , G06F12/0846 , G06F12/128 , G06F12/0842
CPC分类号： G06F12/0848 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0846 , G06F12/0864 , G06F12/12 , G06F12/123 , G06F12/128 , G06F2212/1044 , G06F2212/502
摘要： Systems and methods for dynamically partitioning a shared cache, include dynamically determining a probability to be associated with each one of two or more processors configured to access the shared cache. Based on the probability for a processor, a first cache line of the processor is inserted in a most recently used (MRU) position of a least recently used (LRU) stack associated with the shared cache, pursuant to a miss in the shared cache for the first cache line. Based on the probability for the processor, a second cache line is promoted to the MRU position of the LRU stack, pursuant to a hit in the shared cache for the second cache line. The probability for the processor is determined based on hill-climbing, wherein fluctuations in the probability are reduced, local maxima are prevented, and the probability is prevented from falling below a threshold.
摘要翻译：用于动态分区共享高速缓存的系统和方法包括动态确定与被配置为访问共享高速缓存的两个或更多个处理器中的每一个相关联的概率。基于处理器的概率，根据共享高速缓存中的未命中，将处理器的第一高速缓存行插入与共享高速缓存相关联的最近最少使用（LRU）堆栈的最近使用（MRU）位置中，第一个缓存行。基于处理器的概率，根据用于第二高速缓存行的共享高速缓存中的命中，第二高速缓存行被提升到LRU栈的MRU位置。处理器的概率是基于爬山确定的，其中概率的波动减小，局部最大值被阻止，并且防止概率下降到阈值以下。

23. 发明申请

WO2018048607A1 SELECTIVE APPLICATION OF INTERLEAVE BASED ON TYPE OF DATA TO BE STORED IN MEMORY 审中-公开
标题翻译：基于数据类型的交错式选择性存储在存储器中的应用
公开(公告)号：WO2018048607A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/047773
申请日：2017-08-21
申请人： INTEL CORPORATION
发明人： GREENSPAN, Daniel , FANNING, Blaise
IPC分类号： G06F12/0846 , G11C7/10 , G06F12/0813 , G06F12/0864
CPC分类号： G06F12/0851 , G06F12/0811 , G06F12/0813 , G06F12/0831 , G06F12/0864 , G06F2212/1016 , G06F2212/2515 , G06F2212/283 , G06F2212/502 , G06F2212/601 , G06F2212/621 , G11C7/1072
摘要： Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache entry can include a value in a metadata field indicating an interleave policy. The cache controller can selectively assign the interleave policy to be applied based on a type of data stored in the plurality of cache memories.
摘要翻译：描述了一种设备的技术。该装置可以包括多个高速缓存存储器和高速缓存控制器。高速缓存控制器可以分配高速缓存条目以跨多个高速缓存存储器存储数据。高速缓存条目可以在指示交织策略的元数据字段中包括值。高速缓存控制器可以基于存储在多个高速缓存存储器中的数据的类型来选择性地分配要应用的交织策略。

24. 发明申请

WO2017116927A1 ZERO CACHE MEMORY SYSTEM EXTENSION 审中-公开
标题翻译：零缓存内存系统扩展
公开(公告)号：WO2017116927A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/068166
申请日：2016-12-22
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： CHILIMBI, Trishul A. , RUWASE, Olatunji , SESHADRI, Vivek
IPC分类号： G06F12/0846 , G06F12/0888 , G06F12/128 , G06F9/30 , G06F9/32 , G06F9/38 , G06N3/02
CPC分类号： G06F12/0875 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3812 , G06F9/3826 , G06F12/0848 , G06F12/0888 , G06F12/0893 , G06F12/128 , G06F2212/1016 , G06F2212/1044 , G06F2212/1048 , G06F2212/401 , G06F2212/452 , G06N3/02
摘要： A zero cache memory system extension includes a zero cache to store cache tags associated with zero cache lines, while a corresponding data cache stores cache tags and data bytes associated with non-zero cache lines. As non-zero data is written to the cache, cache lines may be moved from the zero cache to the data cache. Similarly, as zero data is written to the cache, cache lines may be moved from the data cache to the zero cache.
摘要翻译：零高速缓冲存储器系统扩展包括零高速缓存以存储与零高速缓存行相关联的高速缓存标签，而对应的数据高速缓存存储与非零高速缓存行相关联的高速缓存标签和数据字节。当非零数据被写入到高速缓存中时，高速缓存行可能会从零高速缓存移动到数据高速缓存。同样，当零数据写入缓存时，缓存行可能会从数据缓存移至零缓存。

25. 发明申请

WO9945474A2 SPEED-OPTIMIZED CACHE SYSTEM 审中-公开
标题翻译：速度优化缓存系统
公开(公告)号：WO9945474A2
公开(公告)日：1999-09-10
申请号：PCT/DE9900639
申请日：1999-03-07
申请人： PACT INF TECH GMBH , VORBACH MARTIN , MUENCH ROBERT
发明人： VORBACH MARTIN , MUENCH ROBERT
IPC分类号： G06F12/0846 , G06F15/00
CPC分类号： G06F12/0886 , G06F12/0851
摘要： Several cache memories are used instead of a continuously large cache memory. Each memory has a defined address range. A plurality of arithmetic units can access a plurality of cache memories due to the fact that the cache memory is selected on the basis of defined addresses. If several arithmetic units access the same cache memory, one of the arithmetic units undergoes arbitration per time unit and is granted the right of access. If the data is not available in the cache memory, bursting occurs when accessing the memory, that is, a plurality of data is written on a complete line of cache memories (CL) in the memory or read from the memory.
摘要翻译：代替连续广泛的高速缓冲存储器的，多个高速缓冲存储器的使用，每个所述存储器的具有唯一的地址空间。多个算术单元中的可通过高速缓冲存储器访问的多个高速缓冲存储器是基于唯一的地址选择。如果在同一高速缓存存储器中的多个算术单元，每单位时间的运算单元中的一个分别仲裁，并获得访问权。如果在高速缓冲存储器中的数据不是之前，它基本上是在访问存储器时，即gebursted，多个数据被写入超过在存储器高速缓冲存储器（CL）的整行或从存储器中读取。

26. 发明申请

WO2023034661A1 METHODS AND SYSTEMS FOR MEMORY BANDWIDTH CONTROL 审中-公开
公开(公告)号：WO2023034661A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/073925
申请日：2022-07-20
申请人： NUVIA, INC.
发明人： SRINIVASAN, Ramkumar , KUMAR, Amit , GEETHA, Vedaraman , PFLEDERER, Keith Robert , SINHA, Vikas Kumar
IPC分类号： G06F12/0846
摘要： Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

27. 发明申请

WO2023278338A1 DYNAMICALLY COALESCING ATOMIC MEMORY OPERATIONS FOR MEMORY-LOCAL COMPUTING 审中-公开
公开(公告)号：WO2023278338A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/035142
申请日：2022-06-27
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ALSOP, Johnathan , DUTU, Alexandru , AGA, Shaizeen , JAYASENA, Nuwan
IPC分类号： G06F12/02 , G06F12/0855 , G06F12/0879 , G06F15/78 , G06F12/0888 , G06F12/0811 , G06F12/0238 , G06F12/0284 , G06F12/084 , G06F12/0846 , G06F12/0857 , G06F12/0871 , G06F2212/1024 , G06F2212/502
摘要： Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.

28. 发明申请

WO2022039736A1 MEMORY SHARING 审中-公开
公开(公告)号：WO2022039736A1
公开(公告)日：2022-02-24
申请号：PCT/US2020/047025
申请日：2020-08-19
申请人： GOOGLE LLC
发明人： GUPTA, Suyog , NARAYANASWAMI, Ravi , DASARI, Uday Kumar , IRANLI, Ali , THIRUNAGARI, Pavan , KUMAR, Vinu Vijay , KOSIREDDY, Sunitha R.
IPC分类号： G06F12/084 , G06F12/0846 , G06F12/0895 , G06F12/0893
摘要： Components on an IC chip may operate faster or provide higher performance relative to power consumption if allowed access to sufficient memory resources. If every component is provided its own memory, however, the chip becomes expensive. In described implementations, memory is shared between two or more components (110, 114, 116). For example, a processing component (116) can include computational circuitry (206) and a memory (106) coupled thereto. A multi-component cache controller (114) is coupled to the memory (106). Logic circuitry (202) is coupled to the cache controller (114) and the memory (106). The logic circuitry (202) selectively separates the memory (106) into multiple memory partitions (108). A first memory partition (108-1) can be allocated to the computational circuitry (206) and provide storage to the computational circuitry (206). A second memory partition (108-2) can be allocated to the cache controller (114) and provide storage to multiple components (110). The relative capacities of the memory partitions are adjustable to accommodate fluctuating demands without dedicating individual memories to the components.

29. 发明申请

WO2021249029A1 用于执行数据处理的装置、方法、和计算设备审中-公开
公开(公告)号：WO2021249029A1
公开(公告)日：2021-12-16
申请号：PCT/CN2021/088556
申请日：2021-04-21
申请人：华为技术有限公司
发明人：卢廷玉 , 郭海涛 , 李涛 , 俞柏峰
IPC分类号： G06F12/0895 , G06F12/0846
摘要：一种数据处理的装置（110）、方法、和计算设备，所述数据处理装置（110）包括：控制单元（120）和耦合至控制单元（120）的缓存单元（130）。缓存单元（130）利用第一队列（132）和第二队列（134）存储由控制单元（120）接收的多个指令，多个指令包括内存拷贝指令（210）和读写指令（220）。在此，第一队列（132）用于存储内存拷贝指令（210），以及第二队列（134）用于存储读写指令（220）。控制单元（120）接收多个指令，并且根据预定规则（230）和多个指令的类型，将多个指令分别存储至第一队列（132）和第二队列（134）。控制单元（120）并行地执行第一队列（132）和第二队列（134）中存储的指令。由此实现并行地执行两个队列中的指令，进而避免出现读写指令被阻塞的情况。

30. 发明申请

WO2021128505A1 一种与处理器流水线伪同频的ICache实现方法审中-公开
公开(公告)号：WO2021128505A1
公开(公告)日：2021-07-01
申请号：PCT/CN2020/071629
申请日：2020-01-13
申请人：江南大学
发明人：顾晓峰 , 李青青 , 虞致国
IPC分类号： G06F12/0846 , G06F12/0851
摘要：本发明公开了一种与处理器流水线伪同频的ICache实现方法，属于集成电路技术领域。所述方法包括，步骤1：确定ICache的组织结构和工作频率；步骤2：设计ICache的访问和更新策略；步骤3：根据更新策略，确定每个存储体的时钟，保证伪同频ICache一个周期内可填充2*BW位宽的指令数据；步骤4：第一个周期请求访问ICache时，将Data存储体和Tag存储体相应地址的所有路的指令数据和valid+tag取出；步骤5：第二个周期请求访问ICache时，控制电路进行命中判断和Cacheline的有效判断。该方法能够实现ICache在处理器流水线的2分频下工作，且以流水线的时钟频率处理访问请求。

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