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1. 发明申请

WO2017116927A1 ZERO CACHE MEMORY SYSTEM EXTENSION 审中-公开
标题翻译：零缓存内存系统扩展
公开(公告)号：WO2017116927A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/068166
申请日：2016-12-22
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： CHILIMBI, Trishul A. , RUWASE, Olatunji , SESHADRI, Vivek
IPC分类号： G06F12/0846 , G06F12/0888 , G06F12/128 , G06F9/30 , G06F9/32 , G06F9/38 , G06N3/02
CPC分类号： G06F12/0875 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3812 , G06F9/3826 , G06F12/0848 , G06F12/0888 , G06F12/0893 , G06F12/128 , G06F2212/1016 , G06F2212/1044 , G06F2212/1048 , G06F2212/401 , G06F2212/452 , G06N3/02
摘要： A zero cache memory system extension includes a zero cache to store cache tags associated with zero cache lines, while a corresponding data cache stores cache tags and data bytes associated with non-zero cache lines. As non-zero data is written to the cache, cache lines may be moved from the zero cache to the data cache. Similarly, as zero data is written to the cache, cache lines may be moved from the data cache to the zero cache.
摘要翻译：零高速缓冲存储器系统扩展包括零高速缓存以存储与零高速缓存行相关联的高速缓存标签，而对应的数据高速缓存存储与非零高速缓存行相关联的高速缓存标签和数据字节。当非零数据被写入到高速缓存中时，高速缓存行可能会从零高速缓存移动到数据高速缓存。同样，当零数据写入缓存时，缓存行可能会从数据缓存移至零缓存。

2. 发明申请

WO2017116924A1 NEURAL NETWORK TRAINING PERFORMANCE OPTIMIZATION FRAMEWORK 审中-公开
标题翻译：神经网络训练性能优化框架
公开(公告)号：WO2017116924A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/068163
申请日：2016-12-22
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： CHILIMBI, Trishul A. , RUWASE, Olatunji , RAJBHANDARI, Samyam , CARBIN, Michael , HE, Yuxiong
IPC分类号： G06N3/063 , G06N3/08
CPC分类号： G06N3/08 , G06N3/063 , G06N3/084
摘要： A neural network training tool selects from a plurality of parallelizing techniques and selects from a plurality of forward-propagation computation techniques. The neural network training tool performs a forward-propagation phase to train a neural network using the selected parallelizing technique and the selected forward-propagation computation technique based on one or more inputs. Additionally, the neural network training tool selects from a plurality computation techniques and from a plurality of parallelizing techniques for a backward-propagation phase. The neural network training tool performs a backward-propagation phase of training the neural network using the selected backward-propagation parallelizing technique and the selected backward-propagation computation technique to generate error gradients and weight deltas and to update weights associated with one or more layers of the neural network.
摘要翻译：神经网络训练工具从多种并行化技术中选择并从多种前向传播计算技术中进行选择。神经网络训练工具执行前向传播阶段以使用所选择的并行化技术和基于一个或多个输入的所选择的前向传播计算技术来训练神经网络。此外，神经网络训练工具从多个计算技术中选择并从多个并行化技术中选择后向传播阶段。神经网络训练工具执行使用选择的向后传播并行技术和选择的向后传播计算技术来训练神经网络的向后传播阶段，以产生误差梯度和加权增量，并更新与一层或多层神经网络。

3. 发明申请

WO2017116923A1 EFFICIENT INSTRUCTION PROCESSING FOR SPARSE DATA 审中-公开
标题翻译：有效的指令处理对于稀疏数据
公开(公告)号：WO2017116923A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/068162
申请日：2016-12-22
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： CHILIMBI, Trishul A. , RUWASE, Olatunji , SESHADRI, Vivek
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3867 , G06F9/3001 , G06F9/30021 , G06F9/3802 , G06F9/3869 , G06F9/3873
摘要： Efficient instruction processing for sparse data includes extensions to a processor pipeline to identify zero-optimizable instructions that include at least one zero input operand, and bypass the execute stage of the processor pipeline, determining the result of the operation without executing the instruction. When possible, the extensions also bypass the writeback stage of the processor pipeline.
摘要翻译：用于稀疏数据的高效指令处理包括对处理器流水线的扩展以识别包括至少一个零输入操作数的零优化指令，并绕过处理器流水线的执行阶段，确定操作而不执行指令。如有可能，这些扩展还会绕过处理器管道的回写阶段。

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